24 June 2012

Verilog HDL: Usefull Modelling Techniques

Overriding parameters:
 two ways:
à defparam statement
à module_instance parameter value assignments
defparam statement
Eg,:
module hello_world;
parameter id_num =0 ; //define module id=0
initial
        $display (“…….”);
endmodule
module top;
defparam w1.id_num=1, w2.id_num=2;
//change parameter value in the instantiated module
Hello_world w1(); // instantiate two hello_world modules
Hello_world w2();
endmodule

Module Instance Parameter Values:
Eg.:
module top;
Hello_world #(1) w1; //pass value 1 to module w1
Hello_world #(.id_num(2)) w2; // pass value 2 to id_num  parameter for module w2
endmodule

Conditional Compilation:
->use : ‘ifdef,’ifndef,’else,’elseif  and  ‘endif
->these  directives  can  appear  anywhere  in  the  design
->can  conditionally  compile  statements, modules,blocks,declarations  and  other  compiler  directives
->a Boolean  expression  is  not  allowed  with  the  ‘ifdef’  statement

Conditional  Execution :
->all  statements  are  compiled  but  executed  conditionally 
->conditional  execution  flags   can  be  used  only for behavioral statements
->used system task keyword : ->$test$plusargs
                                                  ->$value$plusargs

Time  Scales :
->provides  different delay for modules in a single simulation
Syntax :
 ‘timescale ->/
  ->specifies  the  unit  of measurement  for  times  and  delays
->specifies  the precision to which the delays are rounded  off  during  simulation
->only 1,10  and  100  are  valid  integers for specifying time unit and time precision

1 comment:

  1. Verilog HDL modules are very informatics and very simply describe especially defparam statement, Module Instance Parameter Values, Conditional Execution and Time Scales.

    Asic Design

    ReplyDelete

Your Comments... (comments are moderated)