Using Verilog we can write a test bench to apply stimulus to the design and verify the results of the design. Up-front verification becomes very important as design size increases in size and complexity. This ensures simulation results matches with post synthesis results. A test bench can have two parts, the one generates input signals for the model to be tested while the other part checks the output signals from the design under test.
assign à assign values to registers, wires ; synthesizable and hence used in designs.
force , release: assign and deassign values to wire, reg within procedural block; used in verification
x=1’b0; //generate clock with 20 unit of duty cycle.
#50 $stop; //stop the simulation at time unit 50
//same method is used to generate any inputs
//test bench for full adder
reg ta,tb,tc; //inputs should be held for 20 units; hence declare it as ‘reg’
wire tsum,tcr; //outputs are driven by input. hence ‘wire’
//instantiate the design under test
fulladder fa(.sum(tsum), .cr(tcr), .a(ta), .b(tb), .c(tc));
#0 ta=1’b0; tb=1’b0; tc=1’b0;
#10 ta=1’b0; tb=1’b0; tc=1’b1;
#20 ta=1’b0; tb=1’b1; tc=1’b0;
#30 ta=1’b0; tb=1’b1; tc=1’b1;
#40 ta=1’b1; tb=1’b0; tc=1’b0;
#50 ta=1’b1; tb=1’b0; tc=1’b1;
#60 ta=1’b1; tb=1’b1; tc=1’b0;
#70 ta=1’b1; tb=1’b1; tc=1’b1;
initial $monitor (“$time ta=%b tb=%b tc = %b tsum=%b tcr=%b”, ta,tb,tc,tsum, tcr);
//print the value to console whenener there is a change in the values.