Verilog HDL: Parellel Blocks

Parallel  Blocks :fork, join:
Keywords : fork    
--> statements  in  parallel  block  are  executed   concurrently
--> ordering  of  statement  is  controlled  by  the  delay  or  event  control  assignment  to  each  statement
--> if  delay  or  event  control  is  specified, it  is  relative   to  the  time  the  block  was  entered.
Eg :   
reg  x,y;
                reg  [1:0]  z,w;
                                                X=1’b0;  //completes at simulation time 0
                                                #5  y=1’b1;  //completes  at  simulation  time  5
                                                #10  z={x,y};  //completes  at  simulation time 10
                                                #20  w={y,x};   //completes  at simulation time 20

Force and Release:
à can be used to override assignments on both registers and nets
à nmost commonly used in the interactive debugging process.
à don’t use in design blocks, use only in stimulus or as debug statements.
 #50 force dff.q = 1’b1; //force value of q to 1 at time 50
#50 release dff.q ; //release  the value of q at time  50

#50 force out = a| b &c ;
#50 release out;

Named Blocks:
Blocks  can  be  given  names :
--> local  variables  can  be  declared  for  the  named  block  .
--> Named  blocks  are  a  part  of  the  design  hierarchy variables  in  a  named   block  can be accessed by using hierarchical  name  referencing.
--> Named  blocks  can  be  disabled  i.e, their  execution  can  be  stopped  using  keyword  ‘disable’
Eg :  module  top;
           begin  :block  1
             fork :block 2

Disabling   Named  Blocks :
--> keyword  :disable
--> like   break  in  C
--> disable  allows  disabling   any  named  blocks  in  the  design.

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