04 June 2012

Verilog HDL: Generate Blocks

Generate   Blocks :
--> keywords  :  generate ,  endgenerate
--> Generated   instantiations  can  be  one  or  more  of  the  following  types :
                               --> modules
                               --> user  defined  primitives
                               --> gate  primitives
                                --> continuous  assignments
                                --> initial  and  ‘always’ blocks
There  are  3  methods  to  create  generate  statements :
                                --> generate  loop
                                 --> generate  conditional
                                 --> generate  case
--> generate  are  like  ‘macro’  in  C : will be replaced by actual codes by the simulator
--> ’genvar’  is  a  keyword  used  to declare  variables  that  are  used  only  in  the  evaluation of generate  block.  genvar  do not exist during simulation  of  the design.
--> the value of  ‘genvar’  can be defined  only by  generate  loop
--> generate  loop can be nested .  however  2 generate  loops  using  the  same  ‘genvar’  as  an  index  variable  cannot  be  nested

Generate  Loop :-
//eg : a  bit-wise  XOR  of  two  N-bit  bases
  module  bitwise _xor(out,i0,i1);
parameter  N=32;     //bus  width
output   [N-1 :0]    out;
input  [N-1 : 0]   i0.i1;
genvar  j;          //declare  a  temporary  loop  variable; does  not  exist  during  the  simulation
generate  for  (j=0;j<N;j=j+1)  begin : xor_loop
xor  g1  (out[j],i0[j],i1[j]);
end   //end of  for  loop
endgenerate   //end of generate  block

//alternative  method given  below
reg  [N-1 :0] out;
 generate  for (j=0;j<N;j=j+1)  begin :bit
always @(i0[j]  or  i1[j])    out [j]=i0[j]^i1[j];
endgenerate     */

Generate   Conditional :-
Eg :
          if (a0_width <8) || (a1_width<8)
           Cla_multiplier  #  (a0_width)  mo(product,a0,a1);

Generate  Case :
Eg :  generate
0            : -----------
1            : ------------
default : ----------------

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