### Verilog HDL: Gate Level Modeling

Gate Level Modeling:
à For small number of gate designs;
à Feedbackless structure;
à Used in top level to integrate the design.
Gate –Level Modeling (Structural Modeling):
à mainly includes instantiation of built-in primitives.
à and,nand,or,nor etc

à Design with top-down methodology.
à Implementation with bottom-up methodology.
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

input x,y,z;
output sum,carry;
or o1(.c(carry), .a(c1), .b(c2));
endmodule
﻿
input [3:0] ain,bin;
input cin;
output [3:0] sout,cout;
endmodule

gate level modeling of half Adder:
input a,b;
output s,c;
and a1(c,a,b);     //List of ports
xor x1(s,a,b);      //primitive instatiation; x1 being instatiation label
endmodule;

Gate Level Modelling of Full Adder:
module full_adder(output s, cout, input a,b,cin)
wire s1,cout1,cout2,cout3;
xor x1(s1,a,b);
xor x2(s1,cin);
and a1(cout1,a,b);
and a2(cout2,b,c);
and a3(cout3,c,a);
or o1(cout,cout1,cout2,cout3);
endmodule

Data Flow Modeling:
For small boolean equations; combinational circuits.
module multiplier(port_list)
input IN1, IN2;
output output1;
assign output1=IN1*IN2
endmodule

input a,b;
output s,c;
assign s=a^b;                     //^ àxor
assign c = a&b;                  //& à and
endmodule

a              b             s              c
------------------------------------
0              0              0              0
0              1              1              0
1              0              1              0
1              1              0              1
assignà called as continous assign statement; assignment can only to ‘wire’ not for ‘reg’ data type.
The above type of modeling is called “data flow” modelling.

assignà called as continous assign statement; assignment can only to ‘wire’ not for ‘reg’ data type.
The above type of modeling is called “data flow” modelling.

module full_adder(output s, cout, input a, b, cin);
wire s1;
assign s1=a^b;
assign s=s1^cin;
// can also be coded as s=((a^b)^c));
assign cout=(a&b) | (b&c) | (c&a) ;
endmodule

cin          b             a              s              c
------------------------------------------------
0              0              0              0              0
0              0              1              1              0
0              1              0              1              0
0              1              1              0              1
1              0              0              1              0
1              0              1              0              1
1              1              0              0              1
1              1              1              0              1
Multiplexer:

module mux(z,sel,a,b)
input a,b,sel;
output z;
wire selbar=~sel;
assign z=(a & selbar) | (b & sel);
endmodule

2-Bit Comparator:
module (output g,l,e, input a1,a0,b1,b0)
assign g=({a1,a0}>{b1,b0});
assign l=({a1,a0}<{b1,b0});
assign e=({a1,a0}=={b1,b0});
endmodule

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