24 June 2012

Verilog HDL: Functions And Tasks

Differences :-
 Functions :-
->can  enable  another  function  but  not  another task.
à function always executes in 0 simulation time.
à functions must not contain any delay, event or timing control statements.
-> functions must have atleast one input argument. They can have more than one input.
à functions always returns a single value. They can’t have output or input arguments.
à Delays are not allowed inside function (i.e. @,#,wait).
à Function return only one value.
àwhile’ and ‘forever’ in function are not supported by synthesis tools.
àrepeat’ is supported by some synthesis tools.
àNo procedural blocks like ‘initial’, ‘always’ inside function allowed.
àNo wire in function.
àFunction can call another function but not another task.

8-Bit Parity generator-Behavioural modeling:
redution operators: operate on two successive bits from LSb to MSB
//function to check parity
function parity;
input [7:0] din;
begin
parity=^din; //xor two successive bits from LSB.
end
endfunction

//In main module call the function.
module check_parity (data,x)
input [7:0] data;
output x;
reg x;
always @(data)
begin
x=parity(data);
end

Functions can be within or outside module definition.  But if it is outside the module then it need to be ‘included’ by a compiler directive ‘include’
Syntax: include filename.v
Other compiler directives are:
define à
timescale à to change simulation run time

Tasks:
à a task can enable other tasks and functions.
à tasks may execute in non-zero simulation time
--> tasks may contain delay, event or timing control statements
à tasks may have zero or more arguments of type input, output or inout.
à taskd don’t return with a value, but can pass multiple values through ‘output’ and ‘inout’ arguments.
à Similar to function
à Prefered in testbenches
à Tasks return multiple output values
àTask can call other functions and tasks.

module reg_reversal(din);
input [7:0] din;
reg [7:0] newreg;
always @(din)
begin
newreg=reverse(din);
end

function [7:0] reverse;
input [7:0] din;
integer k;
begin
for (k=0;k=7;k=k+1)
reverse[7-k]=din[k];
end
endfunction
endmodule

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