Gate arrays

2.2.2. Gate arrays

 

In a gate array, the transistors level masks are fully defined and the designer can not change them. The design instead programs the wiring and vias to implement the desired function. For example, Interconnections done in layer anything more than 2. In GA design we take a die which have all gates placed but not connected. Metal 2 layer (interconnect) is available, Only layout of interconnect is given to fabrication house.

 

 Gate array designs are slower than cell-based designs but the implementation time is faster as less time must be spent. RTL-based methods and synthesis, together with other CAD tools, are often used for gate arrays. Efficiency decreases with GA.