Multiple Threshold CMOS (MTCMOS) Circuits

James T. Kao et al. [2] showed MTCMOS logic is effective standby leakage control technique, but difficult to implement since sleep transistor sizing is highly dependent on discharge pattern within the circuit block. They showed dual Vt domino logic avoids the sizing difficulties and inherent performance associated with MTCMOS. High Vt cells are used where leakage has to be prevented whereas low Vt cells are employed where speed is of concern. Both cells are effectively used in MTCMOS technique.

MTCMOS technique [1]

In active mode of operation the high Vt transistors are turned off and the logic gates consisting of low Vt transistors can operate with low switching power dissipation and smaller propagation delay. In standby mode the high Vt transistors are turned off thereby cutting off the internal low Vt circuitry.

Variable Threshold CMOS (VTCMOS)

One of the efficient methods to reduce power consumption is to use low supply voltage and low threshold voltage without loosing speed performance. But increase in the lower threshold voltage devices leads to increased sub threshold leakage and hence more standby power consumption. Variable Threshold CMOS (VTCMOS) devices are one solution to this problem. In VTCMOS technique threshold voltage of the low threshold devices are varied by applying variable substrate bias voltage from a control circuitry.

VTCMOS technique is very effective technique to reduce the power consumption with some drawbacks with respect to manufacturing of these devices. VTCMOS requires either twin well or triple well technology to achieve different substrate bias voltage levels at different parts of the IC. The area overhead of the substrate bias control circuitry is negligible. [1]

References

[1] Sung Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits-Analysis and Design”, Tata McGraw Hill, Third Edition, New Delhi, 2003

[2] James T. Kao and Anantha P. Chandrakasan, “Dual-Threshold Voltage Techniques for Low-Power Digital Circuits”, IEEE Journal Of Solid-state Circuits, Vol. 35, No. 7, pp.1009-1018, July 2000