Answer:
Clock net is one of the High Fanout Net(HFN)s. The clock buffers are designed with some special property like high drive strength and less delay. Clock buffers have equal rise and fall time. This prevents duty cycle of clock signal from changing when it passes through a chain of clock buffers.
Normal buffers are designed with W/L ratio such that sum of rise time and fall time is minimum. They too are designed for higher drive strength.
propagation delay of clock buffer compare to normal buffer for same input transition and same output load is more. why?
ReplyDeleteBecause clock buffer will have the same falling and raising edge
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