Answer:
HFNs are synthesized in front end also.... but at that moment no placement information of standard cells are available... hence backend tool collapses synthesized HFNs. It resenthesizes HFNs based on placement information and appropriately inserts buffer. Target of this synthesis is to meet delay requirements i.e. setup and hold.
For clock no synthesis is carried out in front end (why.....????..because no placement information of flip-flops ! So synthesis won't meet true skew targets !!) ... in backend clock tree synthesis tries to meet "skew" targets...It inserts clock buffers (which have equal rise and fall time, unlike normal buffers !)... There is no skew information for any HFNs.
what is the difference between optimizing for delay and Skew? I think there is no difference between optimizing for delay and skew. while building buffer tree (along with fanout, transition and capacitance) symmetry is also considered where as while in HFN only fanout, transition and capacitance are considered.
ReplyDeleteHi cvn,
ReplyDeleteI agree with you.
HFN synthesis tries to make fanout as less as possible.
While building and optimizing buffer tree special clock buffers are used to make rise and fall transition same so that there is no difference in the duty cycle of the clock. If there is change in duty cycle it will affect skew. (flop to flop delay)
Optimization for delay, i hope you are refereng towards setup and hold, again we insert buffer (or we size cells) in voilating path. Here buffers may have different transition as we try to fix the data path delay with reference to clock.(assuming clock delay(skew) is known or balanced)
rgds
murali
The major design challenges of ASIC design consist of microscopic issues and ... high levels of abstractions, reuse, IP portability, systems on a chip and tool interoperability.synthesis design
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