1. ASIC Synthesis
6.1. Synthesis definition, goals
Synthesis is the process of transforming your HDL design into a gate-level netlist, given all the specified constraints and optimization settings.
Logic synthesis is the process of translating and mapping RTL code written in HDL (such as Verilog or VHDL ) into technology specific gate level representation.
There are 3 steps in Synthesis:
Ø Translation: RTL code is translated to technolohgy independent representation. The converted logic is available in boolean equation form.
Ø Optimization: Boolean equation is optimized using SoP or PoS optimization methods.
Ø Technology mapping: Technology independent boolean logic equations are mapped to technology dependant library logic gates based on design constraints, library of available technology gates. This produces optimized gate level representation which is generally represented in Verilog.
Then the gate level circuit generated is logically optimized to meet the targets or goals set as per the user constraints. The clock frequency target is the number one goal that has to be met by the synthesis operation.