17 June 2013

Synthesizable and Non-Synthesizable Verilog constructs

5.1. Synthesizable and Non-Synthesizable Verilog constructs

Identifiers, escaped identifiers, Sized constants (b, o, d, h), Unsized constants (2'b11, 3'07, 32'd123, 8'hff), Signed constants (s) 3'bs101, module, endmodule, macromodule, ANSI-style module, task, and function port lists
system tasks, real constants
Data types
wire, wand, wor, tri, triand, trior, supply0, supply1, trireg (treated as wire), reg, integer, parameter, input, output, inout, memory(reg [7:0] x [3:0];), N-dimensional arrays,
real, time, event, tri0, tri1
Module instances
Connect port by name, order, Override parameter by order, Override parameter by name, Constants connected to ports, Unconnected ports, Expressions connected to ports,
Delay on built-in gates
Generate statements
if,case,for generate, concurrent begin end blocks, genvar,
and, or, nand, nor, xor, xnor,not, notif0, notif1, buf, bufif0, bufif1, tran,
User defined primitives
(UDPs), table, pullup, pulldown, pmos, nmos, cmos, rpmos, rnmos,
rcmos, tranif0, tranif1, rtran, rtranif0,
Operators and
+, - (binary and unary)
Bitwise operations
&, |, ^, ~^, ^~
Reduction operations
&, |, ^, ~&, ~|, ~^, ^~, !, &&, || , ==, !=, <, <=, >, >=, <<, >>, <<< >>>, {}, {n{}}, ?:, function call
===, !==
Event control
event or, @ (partial), event or using comma syntax, posedge, negedge (partial),
Event trigger (->), delay and wait (#)
Bit and part selects
Bit select, Bit select of array element, Constant part select, Variable part select ( +:, -:), Variable bit-select on left side of an assignment
Continuous assignments
net and wire declaration, assign
Using delay
Procedural blocks
always (exactly one @ required),
Procedural statements
;, begin-end, if-else, repeat, case, casex, casez, default, for-while-forever-disable(partial),
fork, join
Procedural assignments
blocking (=), non-blocking (<=)
force, release
Functions and tasks
Functions, tasks
Compiler directives
`define, `undef, `resetall, `ifndef, `elsif, `line, `ifdef, `else, `endif, `include

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005
[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009
[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009


  1. and what about loops,are they synthesizable?????

    1. If you understand what is verilog you will realize that loops make no sense and serve no purpose.

  2. They are synthesizable as long as they are running for a fixed number of times but not a dynamic value. Ex: for(i=0;i<5;i++) is fine but for(i=0;i<j;i++) is not.

  3. Yes, for and while loops are synthesizable

  4. wand, wor are synthesizable or not?


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