24 June 2012

Verilog HDL: Behavioural Modeling

For complex designs, when algorithms are known.
Behavioural Modeling:
always @ (a,b,sel)
begin
---
---
---
end
always à this block is called structural statement; like cyclic/repetitive behaviour.
@ à event timing control
(a,b,sel) à sensitive list
posedge à +ve edge
negedge à -ve edge
initial à like one shot behaviour/ initialisation purpose; non synthesizable
Sensitivity list should contain all the list of inputs in the combinational circuit. For sequential circuits it is not mandatory. In combinational circuit a missed sensitivity list may violate the functionality of the simulation. But synthesis may be realised properly. Hence we may face simulation and synthesis mismatch.
D-Flip Flop:
always @(posedge clk)
begin
if (rst)                    //i.e.rst == 1’b1
q=1’b0;
else
q=din;
end
endmodule
8 Bitregister Description:
module reg8(q,clk,rst,din)
input clk,rst;
input [7:0] din;
output [7:0] q;
reg [7:0] q;
always @(posedge clk)
begin
if(rst)
q=8’b0;
else
q=din;
end
endmodule
4-Bit Up-Down Counter:
module(q,en,clk,rst,up)
input en,clk,rst,up;
reg [3:0] q;
always @(posedge clk)
begin
if (rst==1’b1)
q=1’b0;
else if (en==1’b1)
if(up==1’b1)
q++;
else if (up==1’b0)
q--;
else if (en==1’b0)
q=1’b0;
end
endmodule

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