24 June 2012

Verilog HDL: Behavioural Description of ALU



Arithmatic: +, -, *, /
Logic: AND, OR, NOT, XOR, XNOR, NAND, NOR
s2            s1            s0            Operation
---------------------------------------------
0              0             0              +
0              0             1             -
0              1             0             *
0              1             1             /
1              0             0             AND
1              0             1             OR
1              1             0             NOT
1              1             1             XOR
always @(ctrl & a & b)
case (ctrl)
begin
0:out=a+b;
1:out=a-b;
2:out=a*b;
3:out=a/b;
4:out=a&b;
5:out=a|b;
6:out=a~b;
7:out=a^b;//xor
default:out=8’b0; //default value =0;
end
Case statement execution is faster than if statement . There are several other advantages of using case statements in RTL coding from the ASIC synthesis point of view.

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