Verilog HDL: Procedural Timing Controls

Procedural Timing   Controls
·         3  methods :   
o   Delay-based  timing  control
o   Event-based  timing  control
o   Level-sensitive  timing  control

Delay-Based  Timing   Control :
·         delays  are  specified  with  symbol  #
·         delay  based  timing  control  can  be  specified  by  a  number, identifier  or  a mintypmax_expression.

3  types  of  delay  control  procedural  statements :
·         Regular  delay  control
·         Intra-assignment  delay  control
·         Zero-delay  control

Regular  Delay  Control:-
·         used  when  a  non-zero  delay  is  specified  to  the  left  of  a  procedural  assignment
Eg :   
parameter   latency =20;       //define  parameters
                parameter  delta=2;
                reg   x,y,z,p,q;        //define  register  variables
                       X=0;       //no  delay  control
                      #10   y=1;     //delay  control  with  a  number.  Delay  execution  of  y=1  by  10 units
                      # latency  z=0;     //delay  control  with  identifier
                      # (latency+delta)  p=1;     //delay  control  with  expression
                      #y  x=x+1;   //delay  control  with  identifier
                      # (4:5:6)  q=0;    //minimum ,  typical  and  maximum  delay  values

Intra-Assignment  Delay  Control :-
·         Delay  is  assigned  to  the  right  of  the  assignment  operator.
Eg :   
 y=#5  x+z;   
 //take  value  of  z  at  time  t=0, evaluate  x+z  and  then  wait  5 time units  to assign
               //value  to y

Zero-Delay  Control :
·         ensures  that  a  statement  is  executed  last, after  all  other  statements  in that simulation  time  are  executed
Eg :   
                        #0  x=1;    //zero   delay  control
                        #0   y=1;

Event   Based  Timing  Control :
·         an  event  is  the  change  in the value on a register  or  a  net
There  are  four  types :
·         regular  event  control
·         named  event  control
·         event  OR control
·         level  sensitive  timing control

Regular  event  control :-
·         @  symbol  is  used
·         statements  can be executed on charges  in signal  value or at a +ve or –ve transition of the signal value
·         the  keywords ‘posedge  and ‘negedge
Eg :-        @ (clock)   q=d;   //q=d  is  executed  whenever  signal  clock changes  value
               @(posedge  clock)  q=d;    //q=d is executed whenever signal clock does a –ve transition (1 to 0,   
                  X to z,  x to 0,z to 0)
                  Q=@(posedge  clock) d;    //d  is  evaluated  immediately and  assigned  to q  at  the +ve edge
                 Of clock.
Named  Event  Control :
·         ’declare’  an  event  and then  ‘trigger’  and  ‘recognize’  the  occurance  of that  event
·         event  does  not  hold  any  data
·         a  named  event  is  declared  by  keyword  ‘event’
·         a  event  is  triggered  by  the  symbol
·         and   recognized  by  the  symbol  @
Eg  :     
 //example  of  a  data  buffer  storing  data  after  the  last  packet  of  data  has  arrived.
event  received_data;    //define an  event  called  received_data
              always  @(posedge  clock)    //check  at  each  +ve  edge
                          if(last_data_packet)   //if  this  is  the  last  data packet
                               ->received_data;     //trigger  the  event  received_ data
                     always  @ (received_data)   //await  triggering of  event  received_data : when  event is
                                                                         //triggered, store all four  packets of received data in data
                                                                        //buffer use concatenation operator { }
                      Data_buf = {data_pkt[0],data_pkt[1],data_pkt[2],data_pkt[3]};

Event   OR  Control :-
Eg :     //a  level  sensitive  latch  with  asynchronous  reset 
              always  @ (reset  or  clock  or  d)       //wait  for  reset  or  clock  or  d  to  change
             //always  @  (reset,clock,d)          
                           if(reset)         //if  reset  signal  is  high,
                                  Q=1’b0;   //set q to  0
                             else if(clock)        //if  clock  is  high, latch  input
Use  :  @*  or  @(*)
·         all  input  variables  are  automatically   included  in  the  sensitivity  list.
Level   Sensitive  Timing  Control :-
·         waits  for  a  certain  condition  to  be  true  before  a  statement  or  a  block  of  statements  is  executed
·         keyword :  wait
Eg :  always
                      wait (count_enable) #20  count=count+1;
           //here count_enable  is  monitored  continuously.  If  count_enable  is  zero, the  statement  is  not    
           //entered.  If  it  is  logical  1,  the  statement  count=count+1  is  executed  after  20  time  units.  If
           //count_enable  stays  at  1,  count  will be  incremented  every  20  time  units.

1 comment:

  1. a very good explanation....and the examples are self explicable....thank you very much...


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