There are 14 logic gates and 12 switches predefined in the Verilog HDL to provide the gate- and switchlevel modeling facility.
- Supports basic logic gates as oredefined primitives.
- and, or, nand, nor, xor, xnor: These gates can have multiple inputs and 1 output.
and a1 (out, in1, in2);
buf, not :These gates have single input and can have multiple output.
buf b1 (out1, out2, in);
-bufif0, bufif1, notif0, notif1 : These gates have 1 input, 1 output and 1 control input.
The following example declares an instance of bufif1:
bufif1 bf1 (out, in, control);
-cmos, nmos, pmos, rcmos, rnmos, rpmos: These are all MOS switches.