Verilog HDL: Hardware Description Using Basic Logic Gates

There are 14 logic gates and 12 switches predefined in the Verilog HDL to provide the gate- and switchlevel modeling facility.
  • Supports basic logic gates as oredefined primitives.
  • and, or, nand, nor, xor, xnor: These gates can have multiple inputs and 1 output.

The following example declares a two-input and gate:

and a1 (out, in1, in2);

The inputs are 'in1' and 'in2'. The output is 'out'. The instance name is 'a1'.

Truth tables of above logic gates are given below.

buf, not :These gates have single input and can have multiple output.

The following example declares a two-output buf:

buf b1 (out1, out2, in);

The input is 'in'. The outputs are 'out1' and 'out2'. The instance name is 'b1'.

Tri-state logic gates:
-bufif0, bufif1, notif0, notif1 : These gates have 1 input, 1 output and 1 control input.

The following example declares an instance of bufif1:

bufif1 bf1 (out, in, control);

The output is 'out', the input is 'in', and the control is 'control'. The instance name is 'bf1'.

-cmos, nmos, pmos, rcmos, rnmos, rpmos: These are all MOS switches.

-pmos - Ptype MOS transistor

-nmos - N type MOS transistor

-rpmos - Resistive P type MOS transisor

-rnmos -Resistive N type MOS transistor

- rtran, rtranif0, rtranif1, tran, tranif0, tranif1: These are bidirectional switches.

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