Tackling advanced DRCs and DPT violations using In-Design flow
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| SNUG India 2015 paper presentation;Photo courtesy: Ananda, Synopsys |
Same paper is presented in this article.
Proceedings of SNUG India 2015 can be found in below link:
SNUG India 2015 Proceedings
Tackling advanced DRCs and DPT
violations using In-Design flow
ABSTRACT
Sub-nano-meter technology
gives more advantages to design community. However along with the advantages it
also brings in lot of challenges along with it. one of them is DRC complacence.
Starting from 20nm lower Metal layers has to be decomposed into two masks and
this requirement gave raise to new set of DRC rules called Double Pattering
Rules commonly known as DPT rules. Along with these rules, regular spacing and
enclosure rules have increased both in numbers and complexity.
Routers can only get us to a reasonable closure on DRCs and due to complex DRCs and DPT violations, fixing DRC violations left by router is highly time consuming and manual process. DRC error fixing at 20nm and below nodes are very complicated and error prone. Manual fixing of DRCs will impact tape-out schedules.
Routers can only get us to a reasonable closure on DRCs and due to complex DRCs and DPT violations, fixing DRC violations left by router is highly time consuming and manual process. DRC error fixing at 20nm and below nodes are very complicated and error prone. Manual fixing of DRCs will impact tape-out schedules.
In this paper, we will talk about In-Design flow using Syopsys’ IC Validator and IC Compiler. This flow helped us in bringing down the DRC counts in an automated process. IC Validator brings the power of complete sign-off quality results as it takes foundry’s qualified sign-off runset and coupled with automatic DRC and DPT repair flow with IC Compiler. This seamless integration between IC Validator and IC Compiler makes stream-in and stream-out process redundant as this interface works completely inside Milkyway/IC Compiler environment.
With In-Design flow, designer can catch DRCs in IC Compiler environment and fix them without going through much of routing topology changes and with no timing impact. This boosts both productivity and tape-out schedules. In this paper we will be presenting impact of In-Design Auto DRC Repair flow on our designs and scope for improving the flow for increased productivity.