Verilog HDL: User-Defined Primitives(UDP)

User-Defined  Primitives(UDP) :

• One of the advanced concepts in verilog
• non synthesizable
• single output many iput
• consume very less memory
• I/Os must be scalar (i.e. bit)
• ‘z’ value is not supported.

primitive myprimitive(c,a,b)

input a,b;

output c;

table

0 0:0

0 1:0

1 0:0

1 1:0

endtable

endprimitive

 

Verilog HDL: Timing and Delays In Verilog

Timing  and  Delays In Verilog:

Path  Delay  Modeling :-

Specify  Blocks :

->a  delay  between  a source  (input  or  inout)  pin  and  a  destination (output  or  inout)  pin   of  a  module  is  called  a   module path delay

->keywords for path delay : ‘specify’,’endspecify’

Eg :

module  m(out,a,b,c,d) ;

output  out;

input  a,b,c,d;

wire  e,f;

specify       //specify  block with path  delay  statements

         (a => out) = 9;  //for  full connection : (a,b*>out) = 9;

         (b=> out) = 9; 

         (c => out) = 11;  //for  full connection : (c,d*>out) = 11;

         (d => out) = 11; 

endspecify

and a1(e,a,b);

and a2(f,c,d);

and a3(out,e,f);

endmodule

Note :

Specify block  is  a  separate  block  in  the  module  and  does  not  appear  under  any  other  block, such  as  initial  or  always.

“specparam”  à  special  parameter  declaration  for  use inside  a specify  block ;  same  as  ‘parameter’   but  only  within  ‘specify’  block.

Rise, fall  and turn off delays :-

->if  only  one  delay  is  specified  , this  value  is  used  for  all  transitions.

->if  two  delays  specified, they  refer  to  the  rise  and fall delay values. The turn-off  delay

Is the minimum of  the  two delays.

->if  all  3  delays  are  specified, they refer  to rise, fall and turn-off delay values.

Eg :   and   #(5)  a1 (out,i1,i2);   //delay  of   5 for all transitions

          and   #(4,6)  a2 (out,i1,i2);  //rise=4,fall=6

          bufif0  #(3,4,5)  b1(out,in,control);   //rise=3,fall=4,turn-off=5

Min/Typ/Max   Values :

Eg1 :  and  #(4:5:6)   a1(out,i1,i2);

Here  4  is minimum  delay(+min delays)

5 is typical  delay(+ty  delays)

6  is  maximum delay(+max  delays)

Eg2 :

and   #(2:3:4,3:4:5,4:5:6)  a3(out,i1,i2);

           Here  2-rise,3-fall,4-turn off  min delays

           3-rise,4-fall,5-turn off  typdelays

            4-rise,5-fall,6-turn off  maxdelays

Timing  checks : $setup  and   $hold :

->$setup,  $hold,  $width

->all  timing  checks  must  be  inside  ‘specify’  blocks

$setup  task  :

$setup (data_event,reference_event,limit);

Data_event : signal that is monitored for violations

Reference_event :  signal that establishes  a  reference  for  monitoring  the  data_event  signal

Limit  :minimum  time  required  for  setup  of  data  event.

$hold   task :

$hold  (reference_event,data_event,limit);

$width  task :

$width (reference_event,limit);

Reference_event : Edge  triggered  event(edge  transition  of  a  signal)

Limit  :  minimum  width  of  the  pulse

Multi Vdd (Voltage)

Dynamic power is directly proportional to power supply. Hence naturally reducing power significantly improves the power performance. At the same time gate delay increases due to the decreased threshold voltage. High voltage can be applied to the timing critical path and rest of the chip runs in lower voltage. Overall system performance is maintained. Different blocks having different voltage supplies can be integrated in SoC. This increases power planning complexity in terms of laying down the power rails and power grid structure. Level shifters are necessary to interface between different blocks.

Multiple Voltage ASIC/SoC Design: Classification

Multi voltage design strategies can be broadly classified as follows [1]:

• Static Voltage Scaling (SVS): Different but fixed voltage is applied to different blocks or subsystems of the SoC design.

• Multi-level Voltage Scaling (MVS): The block or subsystem of the ASIC or SoC design is switched between two or more voltage levels. But for different operating modes limited numbers of discrete voltage levels are supported.

• Dynamic Voltage and Frequency Scaling (DVFS): Voltage as well as frequency is dynamically varied as per the different working modes of the design so as to achieve power efficiency. When high speed of operation is required voltage is increased to attain higher speed of operation with the penalty of increased power consumption.

• Adaptive voltage Scaling (AVS): Here voltage is controlled using a control loop. This is an extension of DVFS.

Multi Voltage Design Challenges

Level Shifters

Signals crossing from one voltage domain to another voltage domain have to be interfaced through the level shifter buffers which appropriately shift the signal levels. Design of suitable level shifter is a challenging job.

Timing Analysis

Timing analysis of the given design becomes simpler with the single voltage as it can be performed for single performance point based on the characterized libraries. Tools can optimize the design for worst case PVT (Process, Voltage, temperature) conditions. This is not the case with multi voltage designs. Libraries should be characterized for different voltage levels that are used in the design. EDA tool has to optimize individual blocks or subsystems and also multiple voltage domains. This analysis becomes complex for larger ASIC/SoC.

Floor planning and Power Planning

Multiple power domain demands multiple power grid structure and a suitable power distribution among them. For a larger ASIC/SoC more careful floor planning and power planning is essential. The speed in which different power domains switch on or off is also important. A low voltage power domain may activate early compared to the high voltage domain. Multi voltage designs pose additional board level complexities. Separate power supply may necessary to provide different power levels.

Multi Voltage Designs: Timing Issues

Clock

Clock Tree Synthesis (CTS) tools should be aware of different power domains and understand the level shifters to insert them in appropriate places. Clock tree is routed through level shifters to reach different power domains. Simultaneous timing analysis and optimization is necessary for multiple voltage domains. Thus CTS becomes more complex in multi voltage designs.

Timing Issues with multi voltage design

Static Timing Analysis (STA)

Timing analysis for single voltage design is easy. When it comes to static voltage scaling it becomes little tougher job as analysis has to be carried out for different voltages. This methodology requires libraries which are characterized for different voltages used. Multi level and dynamic voltage scaling pose a greater challenge. For each supply voltage level or operating point constraints are specified. There can be different operating modes for different voltages. Constraints need not be same for all modes and voltages. The performance target for each mode can vary. EDA tool should be capable of handling all these situations simultaneously to carry out timing analysis. Different constraints at different modes and voltages have to be satisfied.

Multi Voltage Designs: Power Planning Issues

Efficient power planning is one of the key concerns of modern SoC designs. In multi voltage designs providing power to the different power domains is challenging. Every power domain requires independent local power supply and grid structure and some designs may even have a separate power pad. Separate power pad is possible in flip-chip designs and power pad can be taken out near from the power domain. Other chips have to take out the power pads from the periphery which can put limit to the number of power domains.

Local on chip voltage regulation is good idea to provide multiple voltages to different circuits. Unfortunately most of the digital CMOS technologies are not suitable for the implementation of either switched mode of operation or linear voltage regulations. Separate power rail structure is required for each power domain. These additional power rails introduce different levels of IR drop putting limit to the achievable power efficiency.

References

[1] Michael Keating, David Flynn, Robert Aitken, Alan Gibsons and Kaijian Shi, “Low Power Methodology Manual for System on Chip Design”, Springer Publications, NewYork, 2007, www.lpmm-book.org, 4/9/2007