Multiple Threshold CMOS (MTCMOS) Circuits

James T. Kao et al. [2] showed MTCMOS logic is effective standby leakage control technique, but difficult to implement since sleep transistor sizing is highly dependent on discharge pattern within the circuit block. They showed dual Vt domino logic avoids the sizing difficulties and inherent performance associated with MTCMOS. High Vt cells are used where leakage has to be prevented whereas low Vt cells are employed where speed is of concern. Both cells are effectively used in MTCMOS technique.

MTCMOS technique [1]

In active mode of operation the high Vt transistors are turned off and the logic gates consisting of low Vt transistors can operate with low switching power dissipation and smaller propagation delay. In standby mode the high Vt transistors are turned off thereby cutting off the internal low Vt circuitry.

Variable Threshold CMOS (VTCMOS)

One of the efficient methods to reduce power consumption is to use low supply voltage and low threshold voltage without loosing speed performance. But increase in the lower threshold voltage devices leads to increased sub threshold leakage and hence more standby power consumption. Variable Threshold CMOS (VTCMOS) devices are one solution to this problem. In VTCMOS technique threshold voltage of the low threshold devices are varied by applying variable substrate bias voltage from a control circuitry.

VTCMOS technique is very effective technique to reduce the power consumption with some drawbacks with respect to manufacturing of these devices. VTCMOS requires either twin well or triple well technology to achieve different substrate bias voltage levels at different parts of the IC. The area overhead of the substrate bias control circuitry is negligible. [1]

References

[1] Sung Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits-Analysis and Design”, Tata McGraw Hill, Third Edition, New Delhi, 2003

[2] James T. Kao and Anantha P. Chandrakasan, “Dual-Threshold Voltage Techniques for Low-Power Digital Circuits”, IEEE Journal Of Solid-state Circuits, Vol. 35, No. 7, pp.1009-1018, July 2000

Reverse Biased Diode Current (Junction Leakage)-Gate Induced Drain Leakage (GIDL)- Gate Oxide Tunneling

Reverse Biased Diode Current (Junction Leakage)

Parasitic diodes formed between the diffusion region of the transistor and substrate consumes power in the form of reverse bias current which is drawn from the power supply. Junction leakage results from minority carrier diffusion and drift near the edge of depletion regions, and also from generation of electron hole pairs in the depletion regions of reverse-bias junctions. When both n regions and p regions are heavily doped, as is the case for some advanced MOSFETs, there will also be junction leakage due to band-to-band tunneling (BTBT), i.e., electron tunneling from valence band of the p-side to the conduction band of the n-side.

In inverter when input is high NMOS transistor is ON and output voltage is discharged to zero. Now between drain and the n-well a reverse potential difference of Vdd is established which causes diode leakage through the drain junction. The n-well region of the PMOS transistor w.r.to p-type substrate is also reverse biased. This also leads to leakage current at the N-well junction.

The reverse current can be mathematically expressed [2] as,

Ireverse=A.Js.(e^(q.Vbias/kT)-1)

where,
Vbias-->reverse bias voltage across the junction
Js-->reverse satuartion current density
A-->junction area

Gate Induced Drain Leakage (GIDL)

Gate-induced drain leakage (GIDL) is caused by high field effect in the drain junction of MOS transistors. In an NMOS transistor, when the gate is biased to form accumulation layer in the silicon surface under the gate, the silicon surface has almost the same potential as the p-type substrate, and the surface acts like a p region more heavily doped than the substrate. When the gate is at zero or negative voltage and the drain are at the supply voltage level, there can be a dramatic increase of effects like avalanche multiplication and band-to-band tunneling. Minority carriers underneath the gate are swept to the substrate, completing the GIDL path. Higher supply voltage and thinner oxide increase GIDL.

Response of GIDL with varying drain to bulk and gate voltage [1]

Pedram [1] has studied GIDL and has plotted response curve for GIDL with varying drain to bulk and drain to gate voltages as shown in the above figure. From the plot it can be clearly observed that GIDL increases with the increase in V_db and V_dg.

Gate Oxide Tunneling

When there is a high electric field across a thin gate oxide layer gate oxide tunneling of electrons can result in leakage. Electrons may tunnel into the conduction band of the oxide layer; this is called Fowler-Nordheim tunneling. There can also be direct tunneling through the silicon oxide layer if it is less than 3–4 nm thick. Mechanisms for direct tunneling include electron tunneling in the conduction band (ECB), electron tunneling in the valence band (EVB), and hole tunneling in the valence band (HVB). The dominant source of leakage here is direct tunneling of electrons through gate oxide. This current depends exponentially on the oxide thickness and the V_DD [3]

Gate current components flowing between NMOS terminals [3]

References

[1] Massoud Pedram, “Leakage Power Modeling and Minimization”, University of Southern California, Dept. of EE-Systems, Los Angeles, CA 90089, ICCAD 2004 Tutorial, www.ceng.usc.edu, 10/10/2007

[2] Jan M Rabaey, Anantha Chandrakasan and Borivoje Nikolic, "Digital Integrated Circuits A Design Perspective", 2nd Edition, 2005, Prentice Hall

[3] BSIM4.2.1 MOSFET Model, Department of Electrical Engineering and Computer Sciences University of California, Berkeley, 2001

Sub Threshold Current

The sub threshold current always flows from source to drain even if the gate to source voltage is lesser than the threshold voltage of the device. This happens due to the carrier diffusion between the source and drain regions of the CMOS transistor in weak inversion. When gate to source voltage is smaller than but very close to threshold voltage of the device then sub threshold current becomes significant.

As observed by [4] currently, sub threshold leakage is still playing the main part in the three mechanisms. However, researchers believe that gate leakage and reverse-biased junction Band To Band Tunneling (BTBT) will be as important as sub threshold from 45 nm process downwards. In addition, with technology scaling, the gate oxide thickness will be reduced and the substrate doping densities will be increased. As a result other factors such as gate-induced drain leakage (GIDL) and drain-induced barrier lowering (DIBL) will also become more and more evident. Therefore, future effective low leakage design will need to target at several components since all of them play an important role in the total leakage consumption. Various techniques at process and circuit level exist to reduce leakage consumption, including modifying doping profile, oxide thickness and channel length. Forward or inverse body biasing is also one of them, which is a technique resulting in variable threshold CMOS.

Sub threshold current Isub, which occurs when gate voltage is below threshold voltage Vth, is a main part of leakage current [2]. Isub depends on different effects and voltages, which are formulated in following equations [1]:

Where

q is the electrical charge.

T is the temperature,

n is the sub threshold swing coefficient,

kB is the Boltzmann constant,

η is the drain induced barrier lowering (DIBL) coefficient,

γ is the body effect coefficient,

μ is the mobility,

Vth0 is the zero-bias threshold voltage,

Vgs is the gate-source voltage,

Vbs is the bulk-source voltage,

Vds is the drain-source voltage,

εox and εSi are the gate dielectric constants of gate oxide and silicium,

NSUB is the uniform substrate doping concentration and

NDEP the channel doping concentration,

Tox is the thickness of the oxide layer,

ФS is the surface potential,

DSUB and ETA0 are technology dependent DIBL coefficients, and

ETAB is a body-bias coefficient of the BSIM4-Modell.

The delay Td of a CMOS device can be approximated by equation (5).

Where

k’ is a technology constant,

CL is the load, and

α models the short channel effects [3].

Variation of Vth is a common technique to reduce leakage because Isub exponentially scales with Vth (see Equation 1). Thus, higher Vth results in lower leakage. However, from equation (5) follows higher Vth additionally results in longer delay [2]. Hence, optimize the design with the balance application of low Vth (LVT) and high Vth devices (HVT).

Transfer characteristics of MOSFET for VGS near Vth are shown in below figure.

Transfer characteristics of MOSFET V_GS near Vth [2]

From the above figure it can be observed that I_D increases exponentially with reduction in Vth.

As noted by [4] key dependencies of the sub threshold slope can be summarized as follows:

- Tox ↓ =>Cox ↑=> n ↓ =>sharper sub threshold

- NA ↑ =>Csth ↑ =>n ↑ =>softer sub threshold

- VSB ↑ =>Csth ↓ =>n ↓ =>sharper sub threshold

- T ↑ =>softer sub threshold

How to minimize sub threshold leakage?

A increase in the threshold voltage of the device keeps the Vgs of the NMOS transistor safely below the Vt,n. This is the case for logic zero input. For the logic one input increase in the threshold voltage of the device keeps the |Vgs| of the PMOS transistor safely below the |Vt,p|.

References

[1] Anantha P. Chandrakasan, Samuel Sheng and Robert W.Broadersen, “Low Power CMOS Digital Design”, IEEE Journal of Solid State Circuits, vol. 27, no. 4, pp. 472-484, April 1992

[2] Massoud Pedram, “Leakage Power Modeling and Minimization”, University of Southern California, Dept. of EE-Systems, Los Angeles, CA 90089, ICCAD 2004 Tutorial, www.ceng.usc.edu, 10/10/2007

[3] Frank Sill, Frank Grassert and Dirk Timmermann, “Reducing Leakage with Mixed-Vth (MVT)”, 18th International Conference on VLSI Design, IEEE, pp.874-877, January 2005

[4] Wei Liu ,Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey1, Department of Informatics and Mathematical Modeling ,Technical University of Denmark , IMM Technical Report 2007

Leakage Power Trends

Development of the digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. At 90 nm and below, leakage power management is essential in the ASIC design process. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Thinner gate oxides have led to an increase in gate leakage current.

Scaling improves transistor density and functionality on a chip. Scaling helps to increase speed and frequency of operation and hence higher performance. At the same time power dissipation increases. To counteract increase in active and leakage power Vth should also be scaled. Leakage power is catching up with the dynamic power in VDSM CMOS circuits as shown in Figure 1.

Figure 1. Leakage vs.Dynamic power [3]

According to Sung Mo Kang et al.[1] and Anantha P. Chandrakasan et al.[2] power consumption in a circuit can be divided into 3 different components. They are:

1) dynamic

2) static (or leakage) and

3) Short circuit power consumption.

Dynamic (or switching) power consumption occurs when signals which go through the CMOS circuits change their logic state charging and discharging of output node capacitor.

Leakage power consumption is the power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor.

Short circuit power consumption occurs during switching of both NMOS and PMOS transistors in the circuit and they conduct simultaneously for a short amount of time.

Leakage Power

The power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor is considered as leakage power. The leakage power of a CMOS logic gate does not depend on input transition or load capacitance and hence it remains constant for a logic cell.

Figure 2. Leakage power components in an inverter [5]

Leakage Components in Bulk CMOS

Different leakage power components are classified are as follows and are shown in Figure 3.

• Diode reverse bias current or Reverse-biased, drain- and source-substrate junction band-to-band-tunneling (BTBT) –I1
• Sub threshold current – I2
• Gate induced drain leakage – I3

Figure 3. Major leakage components in a transistor [2] [3]

As technology node shrinks towards 45 nm and below gate leakage (i.e. leakage current due to direct tunneling) increases owing to the increased electric field. This is the reason why voltage is scaled down to around 1V. Improvements in the manufacturing process and material have helped to control other leakage components such as sub threshold leakage, GIDL and junction reverse bias leakage. A comparative graphical representation of different leakage currents in different technology nodes is shown in Figure 4.

Figure 4. Technology shrinking vs. Leakage components

Sub threshold leakage is controlled by having more control over threshold voltage. Olden process technologies are causing up to 50 % of threshold voltage variation but newer technologies produce very low threshold voltage deviation, 30 mV being maximum value. Decrease in junction area and voltage automatically decreases junction reverse bias leakage and GIDL respectively. But the tunneling effect is threatening further decrease in device dimension. Reducing the GIDL, reverse bias leakage and gate leakage due to tunneling is directly related to the improvements in fabrication chemistry of the device whereas designer has a little control over threshold voltage. The other way by which a designer can have control over these leakage components is to switch off the device itself in controlled fashion! Low power techniques like “power gating” does this effectively and “back bias” technique controls threshold voltage.

Xiaodong Zhang [3] has studied impact of dynamic and leakage power as technology node reaches deep submicron level. Their summary of the result and leakage trends studied by Massoud Pedram [4] is shown below in Table 1.

Table 1. Leakage power trends

Wide variety of techniques have been developed to address the various aspects of the power problem and to meet power specifications. These techniques include clock gating, multi-threshold (multi-Vt) voltage cells, multiple-voltage domains, substrate biasing, dynamic voltage and frequency scaling (DVFS), power gating. [1]

References

[1] Sung Mo Kang and Yusuf Leblebici, "CMOS Digital Integrated Circuits-Analysis and Design", Tata McGraw Hill, Third Edition, New Delhi, 2003

[2] Anantha P. Chandrakasan, Samuel Sheng and Robert W.Broadersen, “Low Power CMOS Digital Design”, IEEE Journal of Solid State Circuits, vol. 27, no. 4, pp. 472-484, April 1992

[3] Xiaodong Zhang, “High Performance Low Leakage Design Using Power Compiler and Multi-Vt Libraries”, Synopsys, SNUG, Europe, 2003, www.synopsys.com, 10/9/2007

[4] Massoud Pedram, “Leakage Power Modeling and Minimization”, University of Southern California, Dept. of EE-Systems, Los Angeles, CA 90089, ICCAD 2004 Tutorial, www.ceng.usc.edu, 10/10/2007

[5] Michael Keating, David Flynn, Robert Aitken, Alan Gibsons and Kaijian Shi, “Low Power Methodology Manual for System on Chip Design”, Springer Publications, NewYork, 2007, www.lpmm-book.org, 4/9/2007