PVT, Derarting and STA

What is the derate value that can be used?

• For setup check derate data path by 8% to 15%, no derate in the clock path.
• For hold check derate clock path by 8% to 15%, no derate in the data path.

What are the corners you check for timing sign-off? Is there any changes in the derate value for each corner?

• Corners: Worst, Best, Typical.
• Same derating value for best and worst.For typical it can be less.

Write Setup and Hold equtions?

• Setup equation: Tlaunch clock + Tclk-q_max + Tcombo_max <= Tcapute clock - (Tsetup+skew)
• Hold equation: Tlaunch clock + Tclk-q_min + Tcombo_min >= Tcapture clock + (Thold-skew)

Where do you get the WLM's? Do you create WLM's? How do you specify?

• Wire Load Models (WLM) are available from the library vendors.
• We dont create WLM.
• WLMs can be specified depending on the area.

Where do you get the derating value? What are the factors that decide the derating factor?

• Based on the guidelines and suggestions from the library vendor and previous design experience derating value is decided.
• PVT variation is the factor that decides the derating factor.

What factors decides the setup time of flip-flop?

• D- pin transition and clock transition.

Why dont you derate the clock path by -10% for worst corner analysis?

• We can do. But it may not be accurate as the data path derate.