Verilog Test Bench for Asynchronous FIFO

Here is the verilog test bench for the asynchronous FIFO code already published. Simulation results of the asynchronous FIFO will be discussed in coming articles.

//===========================================================

//ta_fifo5.v; test bench for the module a_fifo5

//===========================================================

module ta_fifo5();

parameter f_width=8;

parameter f_depth=16;

wire [f_width-1:0] d_out;

wire f_full_flag,f_half_full_flag,f_almost_full_flag,f_empty_flag,f_almost_empty_flag;

reg [f_width-1:0] d_in;

reg r_en,w_en,r_clk,w_clk;

reg reset;

wire [3:0] r_ptr,w_ptr,ptr_diff;

assign r_ptr=ta_fifo5.r_ptr;

assign w_ptr=ta_fifo5.w_ptr;

assign ptr_diff=ta_fifo5.ptr_diff;

assign r_next_en=ta_fifo5.r_next_en;

assign w_next_en=ta_fifo5.w_next_en;

a_fifo5 ta_fifo5(d_out,f_full_flag,f_half_full_flag,f_empty_flag,

f_almost_full_flag,f_almost_empty_flag,d_in,r_en,w_en,r_clk,w_clk,reset);

initial #5000 $stop;

initial begin #10 r_clk=0; forever #10 r_clk=~r_clk; end

initial begin #5 w_clk=0; forever #50 w_clk=~w_clk; end

//initial begin #10 r_clk=0; forever #50 r_clk=~r_clk; end //test for synchronous operation

//initial begin #10 w_clk=0; forever #50 w_clk=~w_clk; end //test for synchronous operation

initial begin d_in=1;

@(posedge w_en);

repeat(20) @(posedge w_clk) d_in=d_in+2;

repeat(20) @(posedge w_clk) d_in=d_in-1;

end

initial begin reset=1;#30 reset=0;end

initial begin fork #50 w_en=1; #1800 w_en=0; #2500 w_en=1 ; join end

initial begin fork #50 r_en=0; #1850 r_en=1; #2400 r_en=0; #2500 r_en=1; join end

endmodule

//======================================================

// DO file for Modelsim simulator

//This may not applicable for other simulator

//======================================================

vlog a_fifo5.v

vsim a_fifo5

add wave *

force -freeze sim:/a_fifo5/reset 1 0

run

force -freeze sim:/a_fifo5/d_in 00000001 0

force -freeze sim:/a_fifo5/r_en 0 0

force -freeze sim:/a_fifo5/w_en 1 0

force -freeze sim:/a_fifo5/reset 0 0

run

force -freeze sim:/a_fifo5/r_clk 1 0, 0 {10 ns} -r 20

force -freeze sim:/a_fifo5/w_clk 1 0, 0 {50 ns} -r 100

run

force -freeze sim:/a_fifo5/d_in 00000011 0

run

force -freeze sim:/a_fifo5/d_in 00000111 0

run

force -freeze sim:/a_fifo5/d_in 00001111 0

run

force -freeze sim:/a_fifo5/d_in 00011111 0

run

force -freeze sim:/a_fifo5/d_in 00111111 0

run

force -freeze sim:/a_fifo5/d_in 01111111 0

run

force -freeze sim:/a_fifo5/d_in 11111111 0

run

force -freeze sim:/a_fifo5/d_in 11111110 0

run

force -freeze sim:/a_fifo5/d_in 11111100 0

run

force -freeze sim:/a_fifo5/d_in 11111000 0

run

force -freeze sim:/a_fifo5/d_in 11110000 0

run

force -freeze sim:/a_fifo5/d_in 11100000 0

run

force -freeze sim:/a_fifo5/d_in 11000000 0

run

force -freeze sim:/a_fifo5/d_in 10000000 0

run

force -freeze sim:/a_fifo5/d_in 00000000 0

run

force -freeze sim:/a_fifo5/d_in 00000001 0

run

force -freeze sim:/a_fifo5/d_in 00000010 0

run

force -freeze sim:/a_fifo5/w_en 0 0

force -freeze sim:/a_fifo5/r_en 1 0

force -freeze sim:/a_fifo5/d_in 00000011 0

run

force -freeze sim:/a_fifo5/d_in 00000100 0

run

force -freeze sim:/a_fifo5/d_in 00000101 0

run

force -freeze sim:/a_fifo5/d_in 00000110 0

run

force -freeze sim:/a_fifo5/d_in 00000111 0

run

force -freeze sim:/a_fifo5/d_in 8'd8 0

run

force -freeze sim:/a_fifo5/w_en 1 0

force -freeze sim:/a_fifo5/d_in 00001001 0

run

force -freeze sim:/a_fifo5/d_in 00001010 0

run

force -freeze sim:/a_fifo5/d_in 00001011 0

run

force -freeze sim:/a_fifo5/d_in 00001100 0

run

force -freeze sim:/a_fifo5/d_in 00001101 0

run

run

//============================================

Related Articles

• Asynchronous FIFO Design

• FIFO Pointers

• Verilog code for asynchronous FIFO

• New Asynchronous FIFO Design

• Asynchronous FIFO: Simulation and Synthesis

• Asynchronous FIFO-Clock Generation Using DCM