16 February 2008

Physical Design Questions and Answers

  • I am getting several emails requesting answers to the questions posted in this blog. But it is very difficult to provide detailed answer to all questions in my available spare time. Hence i decided to give "short and sweet" one line answers to the questions so that readers can immediately benefited. Detailed answers will be posted in later stage.I have given answers to some of the physical design questions here. Enjoy !

What parameters (or aspects) differentiate Chip Design and Block level design?
  • Chip design has I/O pads; block design has pins.
  • Chip design uses all metal layes available; block design may not use all metal layers.
  • Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.
  • Chip design requires several packaging; block design ends in a macro.

How do you place macros in a full chip design?
  • First check flylines i.e. check net connections from macro to macro and macro to standard cells.
  • If there is more connection from macro to macro place those macros nearer to each other preferably nearer to core boundaries.
  • If input pin is connected to macro better to place nearer to that pin or pad.
  • If macro has more connection to standard cells spread the macros inside core.
  • Avoid criscross placement of macros.
  • Use soft or hard blockages to guide placement engine.

Differentiate between a Hierarchical Design and flat design?
  • Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no subblocks and it has only leaf cells.
  • Hierarchical design takes more run time; Flattened design takes less run time.

Which is more complicated when u have a 48 MHz and 500 MHz clock design?
  • 500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz design.

Name few tools which you used for physical verification?
  • Herculis from Synopsys, Caliber from Mentor Graphics.

What are the input files will you give for primetime correlation?
  • Netlist, Technology library, Constraints, SPEF or SDF file.

If the routing congestion exists between two macros, then what will you do?
  • Provide soft or hard blockage

How will you decide the die size?
  • By checking the total area of the design you can decide die size.

If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
  • Poly

If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
  • Because top two metal layers are required for global routing in chip design. If top metal layers are also used in block level it will create routing blockage.

In your project what is die size, number of metal layers, technology, foundry, number of clocks?
  • Die size: tell in mm eg. 1mm x 1mm ; remeber 1mm=1000micron which is a big size !!
  • Metal layers: See your tech file. generally for 90nm it is 7 to 9.
  • Technology: Again look into tech files.
  • Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc
  • Clocks: Look into your design and SDC file !

How many macros in your design?
  • You know it well as you have designed it ! A SoC (System On Chip) design may have 100 macros also !!!!

What is each macro size and number of standard cell count?
  • Depends on your design.

What are the input needs for your design?
  • For synthesis: RTL, Technology library, Standard cell library, Constraints
  • For Physical design: Netlist, Technology library, Constraints, Standard cell library

What is SDC constraint file contains?
  • Clock definitions
  • Timing exception-multicycle path, false path
  • Input and Output delays

How did you do power planning?
How to calculate core ring width, macro ring width and strap or trunk width?
How to find number of power pad and IO power pads?
How the width of metal and number of straps calculated for power and ground?
  • Get the total core power consumption; get the metal layer current density value from the tech file; Divide total power by number sides of the chip; Divide the obtained value from the current density to get core power ring width. Then calculate number of straps using some more equations. Will be explained in detail later.
How to find total chip power?
  • Total chip power=standard cell power consumption,Macro power consumption pad power consumption.

What are the problems faced related to timing?
  • Prelayout: Setup, Max transition, max capacitance
  • Post layout: Hold

How did you resolve the setup and hold problem?
  • Setup: upsize the cells
  • Hold: insert buffers

In which layer do you prefer for clock routing and why?
  • Next lower layer to the top two metal layers(global routing layers). Because it has less resistance hence less RC delay.

If in your design has reset pin, then it’ll affect input pin or output pin or both?
  • Output pin.

During power analysis, if you are facing IR drop problem, then how did you avoid?
  • Increase power metal layer width.
  • Go for higher metal layer.
  • Spread macros or standard cells.
  • Provide more straps.

Define antenna problem and how did you resolve these problem?
  • Increased net length can accumulate more charges while manufacturing of the device due to ionisation process. If this net is connected to gate of the MOSFET it can damage dielectric property of the gate and gate may conduct causing damage to the MOSFET. This is antenna problem.
  • Decrease the length of the net by providing more vias and layer jumping.
  • Insert antenna diode.

How delays vary with different PVT conditions? Show the graph.
  • P increase->dealy increase
  • P decrease->delay decrease

  • V increase->delay decrease
  • V decrease->delay increase

  • T increase->delay increase
  • T decrease->delay decrease

Explain the flow of physical design and inputs and outputs for each step in flow.

What is cell delay and net delay?

  • Gate delay
  • Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma]

  • Gate delay =function of(i/p transition time, Cnet+Cpin).

  • Cell delay is also same as Gate delay.

  • Cell delay

  • For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

  • Intrinsic delay

  • Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

  • It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor.

  • This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

  • Net Delay (or wire delay)

  • The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

  • It is due to the finite resistance and capacitance of the net.It is also known as wire delay.

  • Wire delay =fn(Rnet , Cnet+Cpin)

What are delay models and what is the difference between them?
  • Linear Delay Model (LDM)
  • Non Linear Delay Model (NLDM)

What is wire load model?
  • Wire load model is NLDM which has estimated R and C of the net.

Why higher metal layers are preferred for Vdd and Vss?
  • Because it has less resistance and hence leads to less IR drop.

What is logic optimization and give some methods of logic optimization.
  • Upsizing
  • Downsizing
  • Buffer insertion
  • Buffer relocation
  • Dummy buffer placement

What is the significance of negative slack?
  • negative slack==> there is setup voilation==> deisgn can fail

What is signal integrity? How it affects Timing?
  • IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues.
  • If Idrop is more==>delay increases.
  • crosstalk==>there can be setup as well as hold voilation.

What is IR drop? How to avoid? How it affects timing?
  • There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop.
  • If IR drop is more==>delay increases.

What is EM and it effects?
  • Due to high current flow in the metal atoms of the metal can displaced from its origial place. When it happens in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro Migration.

  • Affects: Either short or open of the signal line or power line.

What are types of routing?
  • Global Routing
  • Track Assignment
  • Detail Routing

What is latency? Give the types?
  • Source Latency
  • It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".

  • Delay from clock source to beginning of clock tree (i.e. clock definition point).

  • The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

  • Network latency

  • It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".

  • The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

What is track assignment?
  • Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets.

What is congestion?
  • If the number of routing tracks available for routing is less than the required tracks then it is known as congestion.

Whether congestion is related to placement or routing?
  • Routing

What are clock trees?
  • Distribution of clock from the clock source to the sync pin of the registers.

What are clock tree types?
  • H tree, Balanced tree, X tree, Clustering tree, Fish bone

What is cloning and buffering?
  • Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.
  • Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy.


  1. with reference to the question.. "Which is more complicated when u have a 48 MHz and 500 MHz clock design?"
    48 MHz will have more time period and 500 MHz will have less time period, so 500Mz will be more complicated.

    How come 48Mz be complicated.. Can any one elabore this..

    1. Complication is onlybdepend on number of logic levels, how much area timing path exist for example logic cells placed as a group it may not causes to high trans and caps. Technology what we use, example in 130nm cell delays around 200 to 250ps. Same functionaliy cell delays around 10 to 20ps

  2. Hi, Thank you for making a blog with fabulous questoin and answers in back end...
    I have a doubt with reference to the question "calculating the power ring width". From tech file how do we get the maximun metal density of a layer?

    Where is it available???

    Also where the max electromigration value is stored??

  3. Hi cvn,
    Sorry for the typing mistake...You are absolutely right ... 48 and 500 numbers wrongly exchanged...let me correct that !

    Thanks for ur appreciation... participate in discussion and enjoy reading!

    In tf check Layer definitions:

    Layer "M1" {layerNumber=15
    maxCurrDensity = 6.583


  4. Hi Murali,

    Thank you very much for your nice clarification. I have some more doubts with reference to the question "Define antenna problem and how did you resolve these problem?", Can we insert a buffer (to divide the lengthy metal into two)to resolve antenna proble.

    I mean when we insert a buffer we are inserting silicon (along with a little metal). so it can also resolve the problem.

    Are there any disadvantages with this kind of approach?

    Thanks and Regards,

    1. Yes it may causes to setup problem. Antenna violation may comes on small nets with high width also. Generally antenna diodes inserted. Another method is layer hoping.

  5. Hi anil,
    First preference is to metal layer jumping.

    If antenna problem is in lower layer jump to higher layer and again come back.

    If it is in higher layer, well.. you cant jump ! hence use diode.

    Last option,as you said insert buffer. But when you do that higher metal layers has to come to lower metal layer (M1 or M2) to connect to pins of buffer and go back.And also there may not enough place for buffer insertion. (Remember after routing we go for antenna check). This may lead to congestion and DRC voilation.

    In P&R tool you have all these options to fix antenna problem.


  6. Hi Murali,

    While calculating the power consumption, we add up standar cell power, macro power and pad power. How do we know power consumption of all these?


  7. Please refer:



  8. hi can any one help me understanding STA with example if you have any material pls send it to bgsavita@gmail.com it would be great help


  9. Hi, Thanks for this nice material, looking forward for more interesting and deep analysis of different stages of pnr.


  10. can u give the details how to find die area if i know total area from dc compiler.how to estimate die size.can u elaborate on this

  11. Total cell area is obtained from the area report from DC. Take squareroot of this. Obtained value is the approaximate height and width of the core area.

    Total area report provides the area considering pads also. Hence you can estimate what is tha extra area required for the pad.

    Thus you can estimate die size. Remember that this is just an estimate. Actual die size can vary.


  12. Thank u for ur reply.In dc we dont know how much area for net routing.
    u given in example of floor plan using SAMM(systolic array matrix multiplier) floor plan .can u explain on what bases u estimated that.

  13. Since over the cell routing is very common in all EDA tools we need not worry about area required for nets.

    Required Inputs:

    Technology used eg. 0.18 Micron etc
    Total Number of standard cells
    One standard cell area
    Number of IO pads
    Pad height
    Core utilization allowed eg.0.7 (i.e.70 %)


    Total standard cell area = no. of standard cells * one standard cell area (Alternatively this can be directly obtained from the DC area report).

    Core size = Standard cell area / Utilization (Assuming there are no hard macros; If there are then add this also )
    = X um * Y um.

    Die area = [Core width + PG ring width + core offset + 2 * pad height ] *
    [Core height + PG ring width + core offset + 2 * pad height ]
    = A um * B um
    =AB um2

  14. f the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?

    * Because top two metal layers are required for global routing in chip design. If top metal layers are also used in block level it will create routing blockage.

    Here wt is meant by routing blockage ?? can anyone explain me this term??...

    Reply me
    Mujtaba Ahmed

  15. Routing blockage's are used to prevent metal layers get routed in particular chip area.

  16. Can some one explain me wht is the difference between set_input_delay and set_driving_cell in DC?

  17. Why dont we analyze Hold in the Pre CTS stage ?

    1. In preCTS stage, we will see only ideal clock, and anyway tcq delay is greater than thold, there is no sense in checking hold violations at that stage. Generally we won't get any hold violations in preCTS stage.

  18. i need clear explanation about antenna effect and why the name itself antenna effect ,what is the reason how it behaves like a antenna.

  19. can we solve hold violations during prelayout sta

  20. i need some more examples for solving on Setup and hold analysis in Static timing analysis can you please post them....,

  21. 1)What is filler cells? why we use filler cells in Floor Planing/placement?

    1. usually we dont use 100% core area for placing cells.some gaps would be left between those cells.in order to have a power continuity we fill those gaps with filler cells.

  22. 1--Why copper is preferred over aluminum as interconnecting material

    2--Why metal-metal spacing is large than poly-poly spacing
    plz give the references

  23. what are the recent trends in low power vlsi cmos design


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