Intel to Layoff 12000 Job Cut

Intel doing major shake-off, to layoff 12000 of its engineering force from PC business.
According to press release Intel is shifting its focus from PC business to IoT-Internet of Things, Data center, Memory and FPGAs, Connectivity business, Two-in-Ones, Gaming and Home Gateways.

Intel, Best of Luck !

Press Release

Intel Layoffs Are A Sign Of Poor Management

Western Digital Acquires SanDisk

Press release from Western Digital:

"New platform creates  greater scale and ability to deliver extensive portfolio of innovative products and technology

Combined business well-positioned  to capture growth and opportunities created by rapidly evolving storage industry

JV with Toshiba provides stable NAND supply at scale  through a time-tested business model and extends across NVM technologies such as 3D NAND"



Western Digital to buy SanDisk in $19 billion deal

SNUG India 2015 Paper: Tackling advanced DRCs and DPT violations using In-Design flow

I, along with co-author Ananda Veerasangaiah from Synopsys, presented a paper- "Tackling advanced DRCs and DPT violations using In-Design flow" in recently concluded SNUG India 2015, held at Bangalore. The paper can be downloaded below.

Tackling advanced DRCs and DPT violations using In-Design flow

SNUG India 2015 paper presentation;Photo courtesy: Ananda, Synopsys


Same paper is presented in this article.

Proceedings of SNUG India 2015 can be found in below link:
SNUG India 2015 Proceedings

Tackling advanced DRCs and DPT violations using In-Design flow

ABSTRACT



Sub-nano-meter technology gives more advantages to design community. However along with the advantages it also brings in lot of challenges along with it. one of them is DRC complacence. Starting from 20nm lower Metal layers has to be decomposed into two masks and this requirement gave raise to new set of DRC rules called Double Pattering Rules commonly known as DPT rules. Along with these rules, regular spacing and enclosure rules have increased both in numbers and complexity.
Routers can only get us to a reasonable closure on DRCs and due to complex DRCs and DPT violations, fixing DRC violations left by router is highly time consuming and manual process. DRC error fixing at 20nm and below nodes are very complicated and error prone. Manual fixing of DRCs will impact tape-out schedules. 

In this paper, we will talk about In-Design flow using Syopsys’ IC Validator and IC Compiler. This flow helped us in bringing down the DRC counts in an automated process. IC Validator brings the power of complete sign-off quality results as it takes foundry’s qualified sign-off runset and coupled with automatic DRC and DPT repair flow with IC Compiler. This seamless integration between IC Validator and IC Compiler makes stream-in and stream-out process redundant as this interface works completely inside Milkyway/IC Compiler environment.

With In-Design flow, designer can catch DRCs in IC Compiler environment and fix them without going through much of routing topology changes and with no timing impact. This boosts both productivity and tape-out schedules. In this paper we will be presenting impact of In-Design Auto DRC Repair flow on our designs and scope for improving the flow for increased productivity.

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Environmental constraints

14.4. Environmental constraints

Both DRC and optimization constraints follow environmental constraints. Setting up of operating conditions and wire load model falls under environmental constraints.


Timing Constraints

14.3. Timing Constraints




These constraints specify clock related definitions which affect synthesis and timing analysis.

Optimization constraints

14.2 Optimization constraints

Three types of optimizations are possible-area, power and timing. We have optimization constraints related to all these. Synthesis tools assign higher priority to timing constraints over area and power constraints.


Logical DRC constraints

14.1. Logical DRC constraints


DRC constraints exist in library. DRC constraints can’t be relaxed. They can be chosen from library. These constraints are imposed upon the design by requirements specified in the target technology library. This presides over optimization constraints to realize a functional design.


Broadcom to lay-off

Another lay-off in sight in addition to the big one recently announced by Microsoft - Nokia. Broadcom tried to sell its cellular baseband business, ultimately failed to attract anyone ! Earlier Texas Instrument (TI) closed its OMAP platform. We know it is bad for employees, what about VLSI industry as a whole? Are big guys like Qualcomm establishing its monopoly further? Or is that technology is not growing in tandem with benchmark standards? This is not a trend to welcome !

Broadcom to lay off 2,500 employees

Constraints: Clock, Logical DRC, Area, Power


14.    Constraints: Clock, Logical DRC, Area, Power

 
Design constraints are generally specified in “Synopsys Design Constraints” (SDC) form. SDC is very widely used and industry accepted standard for specifying design constraints.

Three types of constraints can be set for the design. They are:

1) Logical DRC constraints
2) Optimization constraints
3) Environmental constraints.

Setup and hold slack


13.    Setup and hold slack

Slack
Slack is defined as difference between actual or achieved time and the desired time for a timing path. For timing path slack determines if the design is working at the specified speed or frequency.



Setup and hold time definition


12.    Setup and hold time definition

Setup and hold checks are the most common types of timing checks used in timing verification. Synchronous inputs (e.g.  D)  have Setup, Hold time specification with respect to the clock input. These checks specify that the data input must remain stable for a specified interval before and after the clock input changes

 

Ø  Setup Time:  the amount of time the data at the synchronous input (D) must be stable before the active edge of clock

Ø  Hold Time: the amount of time the data at the synchronous input (D) must be stable after the active edge of clock.


Both setup and hold time for a flip-flop is specified in the library.

Fundamentals of Timing


1.    Fundamentals of Timing

11.1. Timing paths

Any digital circuit can be represented as a “timing path” modeled between two flip flops.

 

Design Objects


1.    Design Objects

Design objects which are regularly used w.r.to design are design is explained below.