Setup and hold
checks are the most common types of timing checks used in timing verification. Synchronous
inputs (e.g.D)have Setup, Hold time specification with
respect to the clock input. These checks specify that the data input must
remain stable for a specified interval before and after the clock input changes
ØSetup Time:the amount of time the data at the
synchronous input (D) must be stable before the active edge of clock
ØHold Time: the amount of
time the data at the synchronous input (D) must be stable after the active edge
Both setup and hold time for a flip-flop
is specified in the library.
load modeling allows us to estimate the effect of wire length and fanout on the
resistance, capacitance, and area of nets. Synthesizer uses these physical
values to calculate wire delays and circuit speeds. Semiconductor vendors
develop wire load models, based on statistical information specific to the
vendors’ process. The models include coefficients for area, capacitance, and
resistance per unit length, and a fanout-to-length table for estimating net
lengths (the number of fanouts determines a nominal length).
is unavoidable in the everyday operation of a design. Effects on performance
caused by temperature fluctuations are most often handled as linear scaling
effects, but some submicron silicon processes require nonlinear calculations.
The design’s supply voltage can vary from the established ideal
value during day-to-day operation. Often a complex calculation (using a shift
in threshold voltages) is employed, but a simple linear scaling factor is also
used for logic-level performance calculations.
accounts for deviations in the semiconductor fabrication process. Usually
process variation is treated as a percentage variation in the performance
calculation. Variations in the process parameters can be impurity concentration
densities, oxide thicknesses and diffusion depths. These are caused bye non
uniform conditions during depositions and/or during diffusions of the
impurities. This introduces variations in the sheet resistance and transistor
parameters such as threshold voltage. Variations are in the dimensions of the
devices, mainly resulting from the limited resolution of the photolithographic
process. This causes (W/L) variations in MOS transistors.
Wire load models contain informations
that synthnesis tool utilizes to estimate interconnect wiring delays during
logic synthesis phase of the design. Logic library includes several models
approarpriate to different sizes of the design.
This section models the environmental
variations of IC. These are known as Process, Voltage, and temperature
variations. In short it is called PVT.
A set of values of PVT is known as
operating condition. A logic library is characterised for one set of operating
condition. Generally there are different libraries specific to different
operating condition. There are three operating conditions very commonly used in
ASIC synthesis and implementation. Based on the affect on cell delay due to the
variation in PVT these classifications are made.
(also called ‘max’ or ‘slow’)à
library in which cells are characterised for maximum delay
called ‘min’ or ‘fast’)àlibrary
in which cells are characterised for minimum delay
called ‘typical’ or ‘normal’)àlibrary
in which cells are characterised for typical delay
The scaling factors (also called as
K-factors) are multipliers that provide flexibility for derating the delay
values based on PVT.If PVT changes by a
particular value then how to calculate parameter like cell delay or net delay?
using these K-factors that can be accomplished.