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Three types of optimizations are possible-area, power and
timing. We have optimization constraints related to all these. Synthesis tools
assign higher priority to timing constraints over area and power constraints.
DRC constraints exist
in library. DRC constraints can’t be relaxed. They can be chosen from library.
These constraints are imposed upon the design by requirements specified in the
target technology library. This presides over optimization constraints to
realize a functional design.
Another lay-off in sight in addition to the big one recently announced by Microsoft - Nokia. Broadcom tried to sell its cellular baseband business, ultimately failed to attract anyone ! Earlier Texas Instrument (TI) closed its OMAP platform. We know it is bad for employees, what about VLSI industry as a whole? Are big guys like Qualcomm establishing its monopoly further? Or is that technology is not growing in tandem with benchmark standards? This is not a trend to welcome !
Setup and hold
checks are the most common types of timing checks used in timing verification. Synchronous
inputs (e.g.D)have Setup, Hold time specification with
respect to the clock input. These checks specify that the data input must
remain stable for a specified interval before and after the clock input changes
ØSetup Time:the amount of time the data at the
synchronous input (D) must be stable before the active edge of clock
ØHold Time: the amount of
time the data at the synchronous input (D) must be stable after the active edge
Both setup and hold time for a flip-flop
is specified in the library.
load modeling allows us to estimate the effect of wire length and fanout on the
resistance, capacitance, and area of nets. Synthesizer uses these physical
values to calculate wire delays and circuit speeds. Semiconductor vendors
develop wire load models, based on statistical information specific to the
vendors’ process. The models include coefficients for area, capacitance, and
resistance per unit length, and a fanout-to-length table for estimating net
lengths (the number of fanouts determines a nominal length).
is unavoidable in the everyday operation of a design. Effects on performance
caused by temperature fluctuations are most often handled as linear scaling
effects, but some submicron silicon processes require nonlinear calculations.
The design’s supply voltage can vary from the established ideal
value during day-to-day operation. Often a complex calculation (using a shift
in threshold voltages) is employed, but a simple linear scaling factor is also
used for logic-level performance calculations.
accounts for deviations in the semiconductor fabrication process. Usually
process variation is treated as a percentage variation in the performance
calculation. Variations in the process parameters can be impurity concentration
densities, oxide thicknesses and diffusion depths. These are caused bye non
uniform conditions during depositions and/or during diffusions of the
impurities. This introduces variations in the sheet resistance and transistor
parameters such as threshold voltage. Variations are in the dimensions of the
devices, mainly resulting from the limited resolution of the photolithographic
process. This causes (W/L) variations in MOS transistors.