Broadcom to lay-off

Another lay-off in sight in addition to the big one recently announced by Microsoft - Nokia. Broadcom tried to sell its cellular baseband business, ultimately failed to attract anyone ! Earlier Texas Instrument (TI) closed its OMAP platform. We know it is bad for employees, what about VLSI industry as a whole? Are big guys like Qualcomm establishing its monopoly further? Or is that technology is not growing in tandem with benchmark standards? This is not a trend to welcome !

Broadcom to lay off 2,500 employees

Constraints: Clock, Logical DRC, Area, Power

14.    Constraints: Clock, Logical DRC, Area, Power

Design constraints are generally specified in “Synopsys Design Constraints” (SDC) form. SDC is very widely used and industry accepted standard for specifying design constraints.

Three types of constraints can be set for the design. They are:

1) Logical DRC constraints
2) Optimization constraints
3) Environmental constraints.

Setup and hold slack

13.    Setup and hold slack

Slack is defined as difference between actual or achieved time and the desired time for a timing path. For timing path slack determines if the design is working at the specified speed or frequency.

Setup and hold time definition

12.    Setup and hold time definition

Setup and hold checks are the most common types of timing checks used in timing verification. Synchronous inputs (e.g.  D)  have Setup, Hold time specification with respect to the clock input. These checks specify that the data input must remain stable for a specified interval before and after the clock input changes


Ø  Setup Time:  the amount of time the data at the synchronous input (D) must be stable before the active edge of clock

Ø  Hold Time: the amount of time the data at the synchronous input (D) must be stable after the active edge of clock.

Both setup and hold time for a flip-flop is specified in the library.

Fundamentals of Timing

1.    Fundamentals of Timing

11.1. Timing paths

Any digital circuit can be represented as a “timing path” modeled between two flip flops.


Design Objects

1.    Design Objects

Design objects which are regularly used design are design is explained below.

Wire load models for synthesis

9.1. Wire load models for synthesis

Wire load modeling allows us to estimate the effect of wire length and fanout on the resistance, capacitance, and area of nets. Synthesizer uses these physical values to calculate wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on statistical information specific to the vendors’ process. The models include coefficients for area, capacitance, and resistance per unit length, and a fanout-to-length table for estimating net lengths (the number of fanouts determines a nominal length).

Wire load models

1.    Wire load models

Extraction data from already routed designs are used to build a lookup table known as the wire load model (WLM). WLM is based on the statistical estimates of R and C based on “Net Fan-out”.

Operating Condition: Operating Temperature Variation

8.3. Operating Temperature Variation

Temperature variation is unavoidable in the everyday operation of a design. Effects on performance caused by temperature fluctuations are most often handled as linear scaling effects, but some submicron silicon processes require nonlinear calculations.

Operating Condition: Supply Voltage Variation

8.2. Supply Voltage Variation

The design’s supply voltage can vary from the established ideal value during day-to-day operation. Often a complex calculation (using a shift in threshold voltages) is employed, but a simple linear scaling factor is also used for logic-level performance calculations.

Operating Condition: Process Variation

8.1. Process Variation

This variation accounts for deviations in the semiconductor fabrication process. Usually process variation is treated as a percentage variation in the performance calculation. Variations in the process parameters can be impurity concentration densities, oxide thicknesses and diffusion depths. These are caused bye non uniform conditions during depositions and/or during diffusions of the impurities. This introduces variations in the sheet resistance and transistor parameters such as threshold voltage. Variations are in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors.

Operating conditions

1.     Operating conditions

Sources of variation in performance of a chip are due to:

Ø  Process variation (P)

Ø  Supply voltage (V)

Ø  Operating Temperature (T)

.lib: Cell description

7.2.4. Cell description

A cell description in the logic library contains variety of attributes describibing the function, timing, power and any other related information of the cell.

.lib: Wire Load Models Wire Load Models

Wire load models contain informations that synthnesis tool utilizes to estimate interconnect wiring delays during logic synthesis phase of the design. Logic library includes several models approarpriate to different sizes of the design.

.lib: Operating Conditions: Operating Conditions:

This section models the environmental variations of IC. These are known as Process, Voltage, and temperature variations. In short it is called PVT.


A set of values of PVT is known as operating condition. A logic library is characterised for one set of operating condition. Generally there are different libraries specific to different operating condition. There are three operating conditions very commonly used in ASIC synthesis and implementation. Based on the affect on cell delay due to the variation in PVT these classifications are made.

They are:

Ø  worst (also called ‘max’ or ‘slow’)à library in which cells are characterised for maximum delay

Ø  best(also called ‘min’ or ‘fast’)àlibrary in which cells are characterised for minimum delay

Ø  nominal(also called ‘typical’ or ‘normal’)àlibrary in which cells are characterised for typical delay


  /* Operation Conditions */

  nom_process                     : 1.00;

  nom_temperature                 : 125.00;

  nom_voltage                     : 0.95;


  voltage_map (VDD,0.95);

  voltage_map (VSS,0.00);


  define(process_corner, operating_conditions, string);

  operating_conditions (slow) {

    process_corner : "SlowSlow";

    process       : 1.00;

    voltage       : 0.95;

    temperature   : 125.00;

    tree_type     : balanced_tree;

  default_operating_conditions : slow;

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