New Clock Gating Method That Does Not Introduce Clock Skew

FULLY SYNCHRONOUS DESIGN

Fully Synchronous Design (Abbreviated FSD) refers to a digital system having a single clock signal for all Flip Flops (Abbreviated FF) within the system.

In such a design, all FFs are clocked all together by this single clock signal : should a design comprise 1200 FFs, they are clocked together by the same clock signal.

If one is planning an ASIC, then the ASIC manufacturer is responsible for designing a clock tree for his particular die, offering a known (and minimal) clock skew.

The ASIC manufacturer is also responsible for the design of a reset tree for his particular die.

A) MAIN FSD RULES

1-) SINGLE CLOCK: Each and every flip-flop clock input of the whole design is driven by a single clock signal: all clock-input of FFs are connected to the system clock .

Ripple clocking is not allowed, nor clock gating.

Whenever possible, FSDs use a single clock buffer. If more than one clock buffer is required, clock skew is minimized by careful clock tree balancing.

2-) THE SAME ACTIVE EDGE: All FFs in a FSD use the same active edge of the clock. Positive and negative edge triggered FFs may not be mixed in the design.

3-) NO ASYNCHRONOUS RESET/SET: at run time. The asynchronous set/reset of FFs is never activated nor used at "run-time". However each and every FF must be asynchronously reset at power-on, and at Power On only. Resetting a FF or a function (a counter for example) will always be done synchronously at run-time. (Note that using asynchronous reset at run time could make scan path insertion more difficult. Asynchronous reset at run time is a clear invitation for disaster.)

4-) NO LATCHES: FSDs may not use latches, they always use registers. (Latches phohibit scan path insertion.)

5-) NO ASYNCHRONOUS R-S: R-S function using cros-connected gates are not allowed. No feedback in Combinational logic. All feedbacks are registered. R-S function may not be implemented using the asynchronous Set and Reset of Flip Flops. Setting and resetting a FF at run-time must be done synchronously. The R-S function is also synchronous.

6-) External signal must be synchronized before they are used in the system.

As a consequence, in a FSD design, all internal signal transitions happen synchronously, right after the active edge of the system clock. Glitches in the combinational part of the system are also generated right after and only after the edge of the clock.


B) ENABLED DESIGNS.

Enabled designs (abbreviated EDs) are FSDs in which enabled D FFs are extensively used. An enabled D FF, in a FSD environment, is continuously clocked by the system clock. It idles (does not change state) when not enabled, and acts as a normal D FF when enabled. In a FSD environment, this Enable input will also be activated synchronously with the system clock.

In EDs, functions in the system idle continuously, until a one-clock-wide enable signal activates them. I call this « one-clock-wide enabling signal » a TIC. For example, should a counter have to count something, the counter is continuously clocked by the system clock, but TICS makes it count.

In EDs,glitches generated in the combinational parts of the system need not to vanish within a single clock period. In other words, the Q to D path delay may be longer than the receiving FF clock period, as long as the TIC portion of the circuit meets the setup and hold times. For example, a Q to D path delay could be 200 nS, the clock period could be 10 nS, and the system will work if the TIC period is longer than the path delay. This means that path delays may not be analysed against the clock period, but against the TIC period.

Over 99% of FFs in a typical ED is enabled. Only a few FFs in such designs are standard not-enabled FFs.


EDs advantages

Since no asynchronous function is used, combinational glitches have no consequences on the functionality of the system. Glitches need not to be analysed nor taken into account, as long as setup and hold times requirements are met. Knowing that glitches may differ from one implementation to another (e.g. from breadboard to PCB, from FPGA to ASIC or full custom, from one technology to another) ignoring glitches is a major advantage.

Timing analysis is simplified. One may simply make sure that setup and hold times for FFs are not violated. Moreover, enabled functions allow that path delays (the delay from Q output to the next D input through combinational gates) be longer than the clock period of the receiving FFs.

EDs are portable, easily transferred form one technology to another, from discrete to FPGA or ASIC, full custom, finer geometries, etc.
EDs are extremely robust.

Adding a scan path (for test purposes of ASICs) is easy since all FFs already have a single clock source.

Test vectors (for conversion to an ASIC) are easily generated: vectors are compared only once per clock, just before the active edge of the clock. Transitory glitches are ignored since they have no effect on system functionality.

Designing is a lot easier, modifications are easy.

My designs are always FSDs, and EDs.

C) CLOCK GATING VS ENABLED FFs

Many designs use Integrated Clock Gating Cells (ICGC) to lower power consumption. These cells shut down the clock for large parts of a system, saving power. Typical ICGCs gate the system clock, but also introduce clock skew. Gating the clock of a FF is almost like enabling it. A function whose clock has been shut down behaves exactly like a non-enabled function as implemented in EDs.

However a conventional enabled FF, like shown in Fig.1, consumes dynamic power, even if it is not enabled. A more useful approach would be to implement a real clock gating scheme to conserve power, while implementing the essential enabled FF function.

Conventionally, clock gating cells are implemented with a latch and a gate ( And or Nor gate) .

This approach has the major disadvantage of introducing clock skew in the design: FFs having their clock gated are clocked later. This means that gated clock FFs may catch the wrong value while sampling non gated FFs. Delay balancing is a solution but introduces some more risk. A more useful approach would be to have a clock gating method that would not introduce clock skew. Given the fact that a transmission gate, in its conducting state, has virtually zero propagation delay from its input to its output, (It acts like a piece of wire) it appears that a clock gating cell should exploit this characteristic.

The suggested clock gating shown below offers the essential enable function required in EDs, while conserving power. This « gated clock enable » function would be implemented at the FF level. In other words, each FF in a design would come with the gated clock enable function. Dynamic power consumption could be reduced compared to the standard enable FF as shown in Fig.1.

The proposed Gated Clock Enable function has the following advantages

No clock skew is introduced
Reduced power consumption over conventional FFs.

I would like to have  comments from experts on this subject. 

About the Author:

Serge Mathieu 

Retired ASIC designer

Québec QC

Canada

email: smathieu13@hotmail.com