Latest VLSI Back-end Physical Design Interview Questions - Semiconductor Product Company Team 1

I have given below physical design interview questions asked in one of the major semiconductor companies located in Bangalore. This semiconductor giant has multiple independent teams and they evaluate candidates as per their project requirements. Irrespective of the company, these questions are very important if you intend to grow in VLSI(Very Large Scale Integration) physical design domain. 

I welcome answers from my readers for these questions. Best discussions will be published below each questions. In this way please help improve knowledge of the seekers and let this bit help from us may get blessed from those in need. 

These are difficult times due to the impact of COVID-19 pandemic. Updating our knowledge is key for survival and success !!

• What kind of designs you have worked?
• Explain your exposure to FV (Formal Verification), CLP (Conformal Low Power) and IR drop analysis?
• How hierarchical floorplan is done? 
• How sub-HMs (Hard Macros) are integrated?
• How timing is analyzed (with respect to hard macro integration)?
• How clock is balanced (with respect to hard macro integration and hierarchical implementation )?
• Discuss all about hierarchical designs.
• What are the UPF (Unified Power Format , IEEE ( Institute of Electrical and Electronics Engineers,) 1801 ) related issues you faced?
• Imagine you have high frequency design to be closed. Data path logic depth is fine. Your library also supports the frequency you are targeting? If timing is not met how will you approach the issue? How can you converge this design?

Post your answers and discussions in comment section below.