12. Setup and hold time definition
Setup and hold
checks are the most common types of timing checks used in timing verification. Synchronous
inputs (e.g. D) have Setup, Hold time specification with
respect to the clock input. These checks specify that the data input must
remain stable for a specified interval before and after the clock input changes
Ø Setup Time: the amount of time the data at the
synchronous input (D) must be stable before the active edge of clock
Ø Hold Time: the amount of
time the data at the synchronous input (D) must be stable after the active edge
of clock.
Both setup and hold time for a flip-flop
is specified in the library.
Setup
Time is the amount of time the synchronous input (D) must show up, and be
stable before the capturing edge of clock. This is so that the data can be
stored successfully in the storage device.
Setup violations can
be fixed by either slowing down the clock (increase the period) or by
decreasing the delay of the data path logic.
setup information .lib :
timing
() {
related_pin :
"CK";
timing_type :
setup_rising;
fall_constraint(Setup_3_3) {
index_1 ("0.000932129,0.0331496,0.146240");
index_2
("0.000932129,0.0331496,0.146240");
values
("0.035190,0.035919,0.049386", \
"0.047993,0.048403,0.061538",
\
"0.082503,0.082207,0.094815");
}
12.2.
Hold Time
Hold
Time is the amount of time the synchronous input (D) stays long enough after
the capturing edge of clock so that the data can be stored successfully in the
storage device.
Hold
violations can be fixed by increasing the delay of the data path or by
decreasing the clock uncertainty (skew) if specified in the design.
Hold
Information n .lib:
timing () {
related_pin : "CK";
timing_type : hold_rising;
fall_constraint(Hold_3_3) {
index_1
("0.000932129,0.0331496,0.146240");
index_2 ("0.000932129,0.0331496,0.146240");
values ("-0.013960,-0.014316,-0.023648",
\
"-0.016951,-0.015219,-0.034272", \
"0.108006,0.110026,0.090834");
}
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