14 July 2013

Maximum Productivity with Verification IP

 

by Joe Rodriguez, Raghu Ardeishar, and Rich Edelman, Mentor Graphics
When beginning a new design it's common to evaluate how to build a verification infrastructure in the quickest amount of time. Of course it's never just quick to deploy, verification also has to be complete enough to improve confidence in the design. Rapid bring-up and improving the quality of your design are excellent goals. However, you should not forget that your environment should be efficient to use during the verification process. This is where you will spend most of your time, slugging it out day after day. Arguably, debugging design bugs is one of the most time consuming tasks of any project. Transaction Level Modeling (TLM) will change the way you think about debug productivity, especially if you have recently experienced the long and difficult task of deciphering PCIe's training sequences,data transfers and completion codes at the pin level......
Read complete article from Mentor Graphics: Maximum Productivity with Verification IP

No comments:

Post a Comment

Your Comments... (comments are moderated)