29 October 2007

What you mean by scan chain reordering?


Based on timing and congestion the tool optimally places standard cells. While doing so, if scan chains are detached, it can break the chain ordering (which is done by a scan insertion tool like DFT compiler from Synopsys) and can reorder to optimize it.... it maintains the number of flops in a chain.


During placement, the optimization may make the scan chain difficult to route due to congestion. Hence the tool will re-order the chain to reduce congestion.

This sometimes increases hold time problems in the chain. To overcome these buffers may have to be inserted into the scan path. It may not be able to maintain the scan chain length exactly. It cannot swap cell from different clock domains.

Because of scan chain reordering patterns generated earlier is of no use. But this is not a problem as ATPG can be redone by reading the new netlist.


  1. Would you please teach me how to do formal verification between before scan chain reordering and after?

    1. I think, we can set "0" for scan port for both netlist (imp and Golden), before doing formal verification.

    2. Deactivate the Scan control Circuit by giving the constant value to the scan control pins, so that only the pure logic is checked for the equivalence.


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