Some sample questions and anwsers ....
1) What are High-Vt and Low-Vt cells?
Ans: Hvt cells are MOS devices with less leakage due to high Vt but they have higher delay than low VT, where as the low Vt cells are devices, which have less delay, but leakage is high. The threshold (t) voltage dictates the transistor switching speed, it matters how much minimum threshold voltage applied can make the transistor switching to active state, which results to how fast we can switch the transistor. Disadvantage is it needs to maintain the transistor in a minimum sub threshold voltage level to make it switch fast so it leads to leakage of current in turn loss of power.
2) What is useful-skew mean?
Ans: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.
3) Draw Vds-Ids curve for an MOSFET. How it varies with
-->Channel length modulation
4) What is body effect? Write mathematical expression? Is it due to parallel or serial connection of MOSFETs?
Ans1: Increase in Vt (threshold voltage), due to increase in Vs (voltage at source), is called as body effect. It is due to serial connection.
Ans2: In general multiple MOS devices are made on a common substrate. As a result, the substrate voltage of all devices is normally equal. However while connecting the devices serially this may result in an increase in source-to-substrate voltage as we proceed vertically along the series chain (Vsb1=0, Vsb2 0). Which results Vth2>Vth1.
5) What is latch up in CMOS design and ways to prevent it?
Ans1: Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS).
Ans2: Latch-up is a condition in which the parasitic components give rise to the Establishment of low resistance conducting path between VDD and VSS with Disastrous results
6) What is Noise Margin? Relate it with Inverter
After writing this equations draw inverter characteristics curve and show these points in the input and output axis.
7) What happens to delay if you increase load capacitance?Ans: Delay increases.
8) For CMOS logic, give the various techniques you know to minimize power consumption?
Ans: Power dissipation=2fCVDD è minimize the load capacitance C, dc voltage VDD and the operating frequency f.
9) All of us know how an inverter works. What happens when the PMOS and NMOS are interchanged with one another in an inverter?
Ans: O/P will be degraded 1 and degraded 0. (Check with SPICE simulation!)
10) Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits
Ans:1) In digital design, decide the height of standard cells you want to layout. It depends upon how big your transistors will be. Have reasonable width for VDD and GND metal paths. Maintaining uniform Height for all the cell is very important since this will help you use place route tool easily and also incase you want to do manual connection of all the blocks it saves on lot of area.
2) Use one metal in one direction only; this does not apply for metal 1. Say you are using metal 2 to do horizontal connections, and then use metal 3 for vertical connections, metal4 for horizontal, metal 5 vertical etc...
3) Place as much substrate contact as possible in the empty spaces of the layout.
4) Do not use poly over long distances as it has huge resistances unless you have no other choice.
5) Use fingered transistors as and when you feel necessary.
6) Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner.
11) Give two ways of converting a two input NAND gate to an inverter?
(a) Short the 2 inputs of the NAND gate and apply the single input to it.(b) Connect the output to one of the input and the other to the input signal.
12) Convert D-FF into divide by 2.What is the max clock frequency the circuit can handle, given the following information?T_setup= 6nS T_hold = 2nS T_propagation = 10nS
Ans:Circuit: Connect Qbar to D and apply the clk at clk of DFF and take the O/P at Q. It gives freq/2. Max.
Freq of operation: 1/ (propagation delay+setup time) = 1/16ns = 62.5 MHz
13) What is false path? Give an example?
Ans: The paths in the circuit, which are never exercised during normal circuit operation for any set of inputs.Example: give MUX example
14) What are multi-cycle paths? Give example.
Ans: Multi-cycle paths are paths between registers that take more than one clock cycle to become stable.
15) How operating voltage can be used to satisfy timing?
Ans: If multi VDD design then, I feel, we can do something……….. !!
16) How to decide number of pads in chip level design?
Ans: No. of pads= dynamic power / [no. of sides *core voltage * Max current per pad]
17) What is Silicide, salicide, polycide?
Silicide: A fab process
18) Where PVT is referred?
19) Explain ‘slack’ and ‘slew’ with waveforms only.
20) Draw 2 input NOR in transistor level. Draw its layout.
21) Use Euler method to do layout of ((A+B) C)’
22) Draw D latch using MUX.
23) What is spacing, width and overlap rule? Give two examples to each.
24) Why setup is fixed before CTS? Why hold is fixed after CTS?
25) What is the difference between placement and routing congestion?
26) What corner cells contains?
Ans: Nothing………..! It has a metal layer for the continuity of power ground network!
27) What is the difference between core filler cells and metal fillers?
Ans: Core filler cells are used for the continuity of power rails in core area.
Metal fillers are used to avoid Antenna effect. (In DFM).
So ......... thats it...!