11 October 2007

Timing Analysis Interview Questions

  • Why is Hold time neglected while calculating Max Frequency? Why only Setup time is considered?
  • What is capacitive loading? How does it affect slew rate?
  • What is useful-skew mean?
  • What is false path? Give an example?
  • What are multi-cycle paths? Give example.
  • How operating voltage can be used to satisfy timing?
  • How to solve setup and Hold violations in the design
  • What is the difference between local-skew, global-skew and useful-skew?
  • What are the various timing-paths which should be taken care in STA?
  • What is meant by virtual clock definition and why do i need it?
  • What are the various Design constraints used while performing Synthesis for a design?
  • What are set up time and hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
  • What is difference between setup and hold time?
  • Hold time does not depend on clock. Is it true? If so why?
  • What is false path? How it is determined in circuit?
  • What are the affects of false path in a circuit?
  • How power is related with clock frequency?
  • What are multi-cycle paths?
  • Is it possible to reduce clock skew to zero?
  • What is skew, what are problems associated with it and how to minimize it?
  • What is slack?
  • How you can increase clock frequency?
  • What is the significance of contamination delay in sequential circuit timing?
  • What is negative slack? How it affects timing?
  • What is positive slack? How it affects timing?
  • Difference between Synthesis and simulation?
  • What is cell delay and net delay?
  • What are delay models and difference between them.
  • What is wire load model?
  • What does SDC constraints has?

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