20 October 2007

Digital design Interview Questions

  • If inverted output of D flip-flop is connected to its input how the flip-flop behaves?
  • Design a circuit to divide input frequency by 2?
  • Design a divide by two counter using D-Latch.
  • Design a divide-by-3 sequential circuit with 50% duty cycle.
  • What are the different types of adder implementation?
  • Draw a Transmission Gate-based D-Latch?
  • Give the truth table for a Half Adder. Give a gate level implementation of the same.
  • Design an OR gate from 2:1 MUX.
  • What is the difference between a LATCH and a FLIP-FLOP?
  • Design a D Flip-Flop from two latches.
  • Design a 2 bit counter using D Flip-Flop.
  • What are the two types of delays in any digital system
  • Design a Transparent Latch using a 2:1 Mux.
  • Design a 4:1 Mux using 2:1 Mux's.
  • What is metastable state? How does it occur?
  • What is metastablity?
  • Design a 3:8 decoder
  • Design a FSM to detect sequence "101" in input sequence
  • Convert NAND gate into Inverter in two different ways.
  • Design a D and T flip flop using 2:1 mux only.
  • Design D Latch from SR flip-flop.
  • Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
  • What is race condition? How it occurs? How to avoid it?
  • Design a 4 bit Gray Counter?
  • Design 4-bit synchronous counter, asynchronous counter?
  • Design a 16 byte asynchronous FIFO?
  • What is the difference between a EEPROM and FLASH?
  • What is the difference between a NAND-based Flash and NOR-based Flash?
  • Which one is good: asynchronous reset or synchronous reset? Why?
  • Design a simple circuit based on combinational logic to double the output frequency.
  • What is the difference between flip-flop and latch?
  • Implement comparator using combinational logic, that compares two 2-bit numbers A and B. The comparator should have 3 outputs: A > B, A < a =" B.">
  • Give two ways of converting a two input NAND gate to an inverter?
  • What is the difference between mealy and moore state-machines?
  • What is the difference between latch based design and flip-flop based design?
  • What is metastability and how to prevent it?
  • Design a four-input NAND gate using only two-input NAND gates.
  • Why are most interrupts active low?
  • How do you detect if two 8-bit signals are same?
  • 7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?
  • Design all the basic gates NOT, AND, OR, NAND, NOR, XOR, XNOR using 2:1 Multiplexer.
  • How will you implement a full subtractor from a full adder?
  • In a 3-bit Johnson's counter what are the unused states?
  • What is difference between RAM and FIFO?
  • What is an LFSR? List a few of its industry applications.
  • Implement the following circuits:
    (a) 3 input NAND gate using minimum number of 2 input NAND gates
    (b) 3 input NOR gate using minimum number of 2 input NOR gates
    (c) 3 input XNOR gate using minimum number of 2 input XNOR gates assuming 3 inputs A,B,C?
  • Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch?
  • How to implement a Master Slave flip flop using a 2 to 1 mux?
  • How many 2 input xor's are needed to inplement 16 input parity generator?
  • Convert xor gate to buffer and inverter.
  • Difference between onehot and binary encoding?
  • What are different ways to synchronize between two clock domains?
  • How to calculate maximum operating frequency?
  • How to find out longest path?
  • How to achieve 180 degree exact phase shift?
  • What is significance of ras and cas in SDRAM?
  • Tell some of applications of buffer?
  • Implement an AND gate using mux?
  • What will happen if contents of register are shifter left, right?
  • What is the basic difference between analog and digital design?
  • What advantages do synchronous counters have over asynchronous counters?
  • What types of flip-flops can be used to implement the memory elements of a counter?
  • What are the advantages of using a microprocessor to implement a counter rather than the conventional method (flip-flop and logic gates)?
  • What is the principal advantage of Gray Code over straight (conventional) binary?
  • What does Pipelining do?
  • Design divide by 2, divide by 3 circuit with equal duty cycle.
  • How many 4:1 mux do you need to design a 8:1 mux?
  • What is D-Word, Q-word?
  • Define Moore, Mealy state machines. Which one is good for timing?
  • Design a FSM to detect 10110. What is the minimum number of flops required?
  • Design a simple circuit based on combinational logic to double the output frequency.
  • Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)
  • Design a finite state machine to give a modulo 3 counter when x=0 and modulo 4 counter when x=1.
  • Minimize: S= A' + AB
  • What is the function of a D-flipflop, whose inverted outputs are connected to its input?
  • How to synchronize control signals and data between two different clock domains?
  • Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
  • In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
  • How many bit combinations are there in a byte?
  • What are the different Adder circuits you studied?
  • Give the truth table for a Half Adder. Give a gate level implementation of the same.
  • Convert 65(Hex) to Binary
  • Convert a number to its two's compliment and back.
  • What is the 1's and 2's complement of the decimal number 25.
  • If A?B=C and C?A=B then what is the boolean operator ?


  1. Can you also provide answers to the interview questions...that will be useful.

  2. plzzzzzzzz provide answers for above questions.......

  3. yes, I also want to know if there are answers to these ques.

  4. this blog is very interstion. i want more questions with answers plz

  5. If inverted output of D flip-flop is connected to its input how the flip-flop behaves?
    answer = flip flop behaves divide by n circuit.(if one ff is used then inverted output is connected to input then it act as divide by 2 circuit.


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