Below are the important VLSI CMOS interview questions. This set of interview questions may be updated in future. Answers will be posted one by one as and when i prepare them ! Readers are encouraged to post answers in comment section. Here we go.........
Draw Vds-Ids curve for an MOSFET. How it varies with a) increasing Vgs b)velocity saturation c)Channel length modulation d)W/L ratio.
What is body effect? Write mathematical expression? Is it due to parallel or serial connection of MOSFETs?
What is latch-up in CMOS design and what are the ways to prevent it?
What is Noise Margin? Explain with the help of Inverter.
What happens to delay if you increase load capacitance?
Give the various techniques you know to minimize power consumption for CMOS logic?
What happens when the PMOS and NMOS are interchanged with one another in an inverter?
What is body effect?
Why is NAND gate preferred over NOR gate for fabrication?
What is Noise Margin? Explain the procedure to determine Noise Margin
Explain sizing of the inverter?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What happens to delay if we include a resistance at the output of a CMOS circuit?
What are the limitations in increasing the power supply to reduce delay?
How does Resistance of the metal lines vary with increasing thickness and increasing length?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?
Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Give the expression for CMOS switching power dissipation?
Why is the substrate in NMOS connected to ground and in PMOS to VDD?
What is the fundamental difference between a MOSFET and BJT ?
Which transistor has higher gain- BJT or MOS and why?
Why PMOS and NMOS are sized equally in a Transmission Gates?
What is metastability? When/why it will occur? What are the different ways to avoid this?
Explain zener breakdown and avalanche breakdown?
* What happens if Vds is increased over saturation?
In the I-V characteristics curve, why is the saturation curve flat or constant? What happens if a resistor is added in series with the drain in a CMOS transistor? What are the different regions of operation in a CMOS transistor? What are the effects of the output characteristics for a change in the beta (β) value? What is the effect of body bias? What is hot electron effect and how can it be eliminated? What is channel length modulation? What is the effect of temperature on threshold voltage? What is the effect of temperature on mobility? What is the effect of gate voltage on mobility? What are the different types of scaling? What is stage ratio? What is charge sharing on a bus? What is electron migration and how can it be eliminated? Can both PMOS and NMOS transistors pass good 1 and good 0? Explain. Why is only NMOS used in pass transistor logic? What are the different methodologies used to reduce the charge sharing in dynamic logic? What are setup and hold time violations? How can they be eliminated? Explain the operation of basic SRAM and DRAM. Which ones take more time in SRAM: Read operation or Write operation? Why? What is meant by clock race? What is meant by single phase and double phase clocking? If given a choice between NAND and NOR gates, which one would you pick? Explain. Explain the origin of the various capacitances in the CMOS transistor and the physical reasoning behind it. Why should the number of CMOS transistors that are connected in series be reduced? What is charge sharing between bus and memory element? What is crosstalk and how can it be avoided? Realize an XOR gate using NAND gate. What are the advantages and disadvantages of Bi-CMOS process? Draw an XOR gate with using minimum number of transistors and explain the operation. What are the critical parameters in a latch and flip-flop? What is the significance of sense amplifier in an SRAM? Explain Domino logic. What are the advantages of depletion mode devices over the enhancement mode devices? How can the rise and fall times in an inverter be equated? What is meant by leakage current? Realize an OR gate using NAND gate. Realize an NAND gate using a 2:1 multiplexer. Realize an NOR gate using a 2:1 multiplexer. Draw the layout of a simple inverter. What are the substrates of PMOS and NMOS transistors connected to and explain the results if the connections are interchanged with the other. What are repeaters? What is tunneling problem? What is meant by negative biased instability and how can it be avoided? What is Elmore delay algorithm? What is meant by metastability? What is the effect of Vdd on delay? What is the effect of delay, rise and fall times with increase in load capacitance? What is the value of mobility of electrons? What is value of mobility of holes? Give insights of an inverter. Draw Layout. Explain the working. * Give insights of a 2 input NOR gate. Draw Layout. Explain the working.
Give insights of a 2 input NAND gate. Draw layout. Explain the working? Implement F= not (AB+CD) using CMOS gates. What is a pass gate. Explain the working? Why do we need both PMOS and NMOS transistors to implement a pass gate? What does the above code synthesize to? Draw cross section of a PMOS transistor. Draw cross section of an NMOS transistor. What is a D-latch? Implement D flip-flop with a couple of latches? Implement a 2 input AND gate using transmission gate? Explain various adders and difference between them? How can you construct both PMOS and NMOS on a single substrate? What happens when the gate oxide is very thin? What is SPICE? What are the differences between IRSIM and SPICE? What are the differences between netlist of HSPICE and Spectre? Implement F = AB+C using CMOS gates? What is hot electron effect? Define threshold voltage? List out the factors affecting power consumption on a chip? What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths? What is clock feed through? Implement an Inverter using a single transistor? What is Fowler-Nordheim Tunneling? Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why? Draw the Differential Sense Amplifier and explain its working. How to size this circuit? What happens if we use an Inverter instead of the Differential Sense Amplifier? Draw the SRAM Write Circuitry How did you arrive at sizes of transistor in SRAM? How does the size of PMOS pull up transistors for bit and bitbar lines affect SRAM’s performance? What is the critical path in a SRAM? Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal? Give a big picture of the entire SRAM layout showing placements of SRAM cells, row decoders, column decoders, read circuit, write circuit and buffers. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
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helped me a lot over timing analysis.... thank you for the posts... looking ahead for the answers to the interview questions..
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