Latest VLSI Back-end Physical Design Interview Questions - Semiconductor Product Company Team 2 and 3

Interview Questions from Major Semiconductor Product Company Team 2:

(These questions were asked by tech lead with ~6-10 years of experience)

• What are PLL related specification for placement?
• What is static IR drop?
• What are different types of dynamic IR?
• Is it average, peak to peak? Or RMS? What are all these?

Interview Questions from Major Semiconductor Product Company Team 3:

(Here interviewer seems to be senior sign-off STA engineer with more than 15 years of industry experience)

• What are different floor-planning approach?
• How feed-through information is processed? How feed-through clocks are handled?
• What is the problem with high insertion delay if timing is met? What is the problem with high skew if timing is met?
• Assume you have to tape-out tomorrow… You just found that there was an issue in constraint . That is false path applied on real path.  What you will do fix timing if it violates timing?
• Assume you have taped out. Silicon has come. Later you found that certain logic is not meeting hold? What can you tell to chip testing team to overcome issue? 
• You have idea of binning?
• Assume 5ns is clock period. You have one single cycle path failing by -50ps. MCP failing by -90ps and half cycle failing by -45ps. Which is one critical here? Which one you will fix?
• There is path: +ve edge triggered flop 1 à then a +ve latch à then a +ve edge triggered flop 2; all clocked by same clock. What will be output of flop2?