What is the difference between Formal verification and Logic verification?
What are stuck-at faults?
What is meant by ATPG?
What is the difference between verification and validation? And what are procedures of doing the same?
What is the difference between testing and verification?
For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?
Explain about stuck at fault models, scan design, BIST and IDDQ testing?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
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