Physical Design


1. Physical Design Flow

2. Libraries In Physical Design

Physical Library

Technology File Libraries

Unit Tile

Cell Libraries

Standard Cell Libraries

I/O cell (pad cell) Libraries

Special (Custom or Macro) Cell libraries

3. Inputs–outputs to/from Different  RTL to GDS design process

4. Data Setup

5. Floorplanning

Floorplanning (Die) Size

Core utilization

Core to I/O clearence

Row configuration:

Cell orientation

Pad Limited Design

Core Limited Design

Bond Pads

Corner Cells

Pad fillers

IO Pad Placement

IO Pin Placement

Hard Macro Placement

Macro Placement guidelines

Flight-lines (Fly-lines)


Placement Blockages

Routing Blockages

6. Power planning and management

Core Power Ring

Vertical and Horizontal Straps

Pad Power Ring

PAD to core ring power strap

Power rails

Power Planning Equations

Some Power Planned Chip Examples

7. Placement

Special Cell Placement

Well-Tap Cells and  End-Cap Cells

Spare Cells

Decap Cells

JTAG and Other Cells Close to the I/Os

Optimizing and Reordering Scan Chains

Plaement Methodology

Congestion Driven Placement

Timing Driven Placement

Logic optimization In Placement

Major Placement Steps

Virtual Placement

HFN synthesis

Initial (Global) Placement

Detailed placement (Legalization) –Refine Placement

Postplacement Analysis- Timing, Congestion Analysis

Placement Congestion: cell density   

Global Route Congestion

8. Clock Tree Synthesis

Goals of CTS

Clock Tree Begin and End

How to Handle Hard Macros

Clock Buffers and Inverters

Skew Balancing

Pre-CTS Clock

CTS Algorithms

Clock tree optimization

Post CTS Clock Tree Structure

Clock design problems

9. Routing

Grid Based Routing

Prefered Routing Direction

Unit Tie

Non Default Routing Rules

Global routing

Global Routing Cells

Global Routing Congestion

Track Assignment
Detail Routing

Search and Repair

10. Physical DRC Verification

Micron rules

Lamda rules

Minimum Width

Minimum Spacing

Minimum Enclosure

Minimum Extension

11. Design For Manufacturability

Antenna Fixing

Solutions for Antenna Violations

Critical Area

Wire Spreading

Via Reliability

Double Via Insertion

Metal Fill Insertion

Filler Cell Insertion

12. Engineering Change Order (ECO)

Non-Freeze Silicon (Unconstrained)  ECO (Pre-Mask ECO)

Freeze Silicon ECO (Post Mask ECO)



  1. VSD is an IIT Bombay Alumnus initiative which plays a role of bridging up the gap between the Concepts learned in Graduate School to the Knowledge applied in Industrial World. Building a Chip is like building a City. And the most important part of any Structure is the base i.e. Basic and Fundamentals of the CHIP Design.
    Our idea is to build an Eco-System for Knowledge Sharing. We have tried to squeeze in the concepts related to Chip design, Physics of Semiconductor and Industrial flow into very simple Infographics Macro video.
    Below link has the introductory lectures.
    VSD Team

  2. Hi Team,

    Its a nice blog.
    Where can i get to read more about each topics in the content listed above


  3. Hi can i get the reference books for the above topics

  4. can i found this topics anywhere in depth.......plz reply me..


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