tag:blogger.com,1999:blog-2516717450266481889.post2367527862575104166..comments2024-03-22T12:53:39.867+05:30Comments on ASIC-System on Chip-VLSI Design: Verilog HDL: Test Bench for 4-Bit AdderMuralihttp://www.blogger.com/profile/05927561262168582763noreply@blogger.comBlogger1125tag:blogger.com,1999:blog-2516717450266481889.post-89945247156781374532014-03-12T10:36:34.028+05:302014-03-12T10:36:34.028+05:30 begin
#0 ta=4’b0000; tb=4’b0000; tc=1’b0;
#10 ta=... begin<br />#0 ta=4’b0000; tb=4’b0000; tc=1’b0;<br />#10 ta=4’b0100; tb=4’b0011; tc=1’b1;<br />#20 ta=4’b0011; tb=4’b0111; tc=1’b1;<br />#30 ta=4’b1000; tb=4’b0100; tc=1’b0;<br />#40 ta=4’b0101; tb=4’b0101; tc=1’b1;<br />(or we can also write : #10 ta=4’d5; tb=4’d6; tc=1’d1;)<br />end<br /><br />how to calc this??adminhttps://www.blogger.com/profile/08714544651350871103noreply@blogger.com