02 July 2013

How hardware is inferred?


5.2. How hardware is inferred?

5.2.1 Register inference


Whenever there is a ‘posedge’ or ‘negedge’ construct synthesis tool infers a flip flop.

 

always @(posedge clk)

output_reg <= data;

 

Above code infers D-flip flop.

 

Asynchronous reset :

 

module async_rst(clk,rst,data,out);

input clk, rst, data;

output out;

reg out;

 

always @(posedge clk or negedge rst)

begin

if(!rst)

out<=1’b0;

else    

out<=data;

end

endmodule

 

In above case the sensitivity list includes both clock and the rst and hence it infers a asynchronous reset flip flop. rst has negedge in sensitivity list and hence same should be checked in the code.

 

Synchronous Reset:

 

module sync_rst(clk,rst,data,out);

input clk, rst, data;

output out;

reg out;

 

always @(posedge clk)

begin

if(!rst)

out<=1’b0;

else

out<=data;

end

endmodule

 

In above case the sensitivity list doesn’t include ‘rst’ and hence it infers a synchronous reset flip flop.

 

5.2.2 Mux Inference

“if else” loop infers a mux. 

eg.:

 if(sel) z=a; else z=b;

 

General case statement infers a mux. If case statement is a overlapping structure then priority encoder in infered.  Case statements only works with true values of 0 or 1.

 

 

5.2.3. Priority Encoder Inference

Multiple if statements with multiple branches result in the creation of priority encoder structure.

“if else if” infers priority encoder.

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