17 June 2013

Synthesizable and Non-Synthesizable Verilog constructs

5.1. Synthesizable and Non-Synthesizable Verilog constructs

Identifiers, escaped identifiers, Sized constants (b, o, d, h), Unsized constants (2'b11, 3'07, 32'd123, 8'hff), Signed constants (s) 3'bs101, module, endmodule, macromodule, ANSI-style module, task, and function port lists
system tasks, real constants
Data types
wire, wand, wor, tri, triand, trior, supply0, supply1, trireg (treated as wire), reg, integer, parameter, input, output, inout, memory(reg [7:0] x [3:0];), N-dimensional arrays,
real, time, event, tri0, tri1
Module instances
Connect port by name, order, Override parameter by order, Override parameter by name, Constants connected to ports, Unconnected ports, Expressions connected to ports,
Delay on built-in gates
Generate statements
if,case,for generate, concurrent begin end blocks, genvar,
and, or, nand, nor, xor, xnor,not, notif0, notif1, buf, bufif0, bufif1, tran,
User defined primitives
(UDPs), table, pullup, pulldown, pmos, nmos, cmos, rpmos, rnmos,
rcmos, tranif0, tranif1, rtran, rtranif0,
Operators and
+, - (binary and unary)
Bitwise operations
&, |, ^, ~^, ^~
Reduction operations
&, |, ^, ~&, ~|, ~^, ^~, !, &&, || , ==, !=, <, <=, >, >=, <<, >>, <<< >>>, {}, {n{}}, ?:, function call
===, !==
Event control
event or, @ (partial), event or using comma syntax, posedge, negedge (partial),
Event trigger (->), delay and wait (#)
Bit and part selects
Bit select, Bit select of array element, Constant part select, Variable part select ( +:, -:), Variable bit-select on left side of an assignment
Continuous assignments
net and wire declaration, assign
Using delay
Procedural blocks
always (exactly one @ required),
Procedural statements
;, begin-end, if-else, repeat, case, casex, casez, default, for-while-forever-disable(partial),
fork, join
Procedural assignments
blocking (=), non-blocking (<=)
force, release
Functions and tasks
Functions, tasks
Compiler directives
`define, `undef, `resetall, `ifndef, `elsif, `line, `ifdef, `else, `endif, `include

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005
[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009
[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

RTL Coding for Logic Synthesis

5. RTL Coding for Logic Synthesis


[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005
[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009
[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009

16 June 2013

Major EDA Companies and their tools

4. Major EDA Companies and their tools

Overview of Complete ASIC Design Flow

3. Overview of Complete ASIC Design Flow

Front End VLSI Design Flow 

Netlist To GDS Flow


FPGA-ASIC Design Advantages-Disadvantages

2.4.1 FPGA Design Advantages

  • Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA ! Done !!
  • No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. (sometimes its free ! You need to buy FPGA.... thats all !). For ASIC you pay huge NRE and tools are expensive. I would say "very expensive"...Its in crores....!!
  • Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis.

  • More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device.

  • Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features.

  • Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again.Modern FPGAs are reconfigurable both partially and dynamically.

  • FPGAs are good for prototyping and limited production.If you are going to make 100-200 boards it isn't worth to make an ASIC.

  • Generally FPGAs are used for lower speed, lower complexity and lower volume designs.But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design.

  • Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ?

  • FPGA sythesis is much more easier than ASIC.

  • In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it.

2.4.2. FPGA Design Disadvantages

  • Power consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race !

  •  You have to use the resources available in the FPGA. Thus FPGA limits the design size.

  •  Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation.

2.4.3. ASIC Design Advantages

  • Cost....cost....cost....Lower unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA.

  • Speed...speed...speed....ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations.

  •       Low power....Low power....Low power: ASIC can be optimized for required low power. There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life !!

  • In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA.

  • In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no need of DFT !) .

2.4.4. ASIC Design Disadvantages

  • Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC.

  • Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!)
  • Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE.


2.4. FPGA vs. ASIC

Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons but it is designers responsibility to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs.


Standard Cell ASIC Vs Gate Array Vs FPGA

2.3. Standard Cell ASIC Vs Gate Array Vs FPGA

Standard Cell ASIC Vs Gate Arrays Vs FPGA


2.2.2. FPGA

FPGA-Field Programmable Gate Arrays
Field Programmable Gate Array (FPGA) are off-the-shelf ICs that can be programmed by the user to capture the logic. There are no custom mask layers so final design implementation is a few hours instead of a few weeks. Simple FPGAs are used for simple functions.
·         FPGAs are increasingly displacing standard cell designs.
·         Capable of capturing 100,000+ designed gates
·         High power consumption
·         High per-unit cost
·         FPGAs are also slow (< 100 MHz)

Gate arrays

2.2.2. Gate arrays

In a gate array, the transistors level masks are fully defined and the designer can not change them. The design instead programs the wiring and vias to implement the desired function. For example, Interconnections done in layer anything more than 2. In GA design we take a die which have all gates placed but not connected. Metal 2 layer (interconnect) is available, Only layout of interconnect is given to fabrication house.
 Gate array designs are slower than cell-based designs but the implementation time is faster as less time must be spent. RTL-based methods and synthesis, together with other CAD tools, are often used for gate arrays. Efficiency decreases with GA.

Standard cell based ASIC design

2.2.1 Standard cell based ASIC design

09 June 2013

Semi-custom IC Design

2.2.Semi-custom IC Design

01 June 2013

Full Custom IC Design

2.1 Full Custom IC Design


IC Design Methodologies

1.     IC Design Methodologies

SoC Design Issues

1.2. SoC Design Issues