Verilog HDL: Timing and Delays In Verilog

Timing  and  Delays In Verilog:

Path  Delay  Modeling :-

Specify  Blocks :

->a  delay  between  a source  (input  or  inout)  pin  and  a  destination (output  or  inout)  pin   of  a  module  is  called  a   module path delay

->keywords for path delay : ‘specify’,’endspecify’

Eg :

module  m(out,a,b,c,d) ;

output  out;

input  a,b,c,d;

wire  e,f;

specify       //specify  block with path  delay  statements

         (a => out) = 9;  //for  full connection : (a,b*>out) = 9;

         (b=> out) = 9; 

         (c => out) = 11;  //for  full connection : (c,d*>out) = 11;

         (d => out) = 11; 

endspecify

and a1(e,a,b);

and a2(f,c,d);

and a3(out,e,f);

endmodule

Note :

Specify block  is  a  separate  block  in  the  module  and  does  not  appear  under  any  other  block, such  as  initial  or  always.

“specparam”  à  special  parameter  declaration  for  use inside  a specify  block ;  same  as  ‘parameter’   but  only  within  ‘specify’  block.

Rise, fall  and turn off delays :-

->if  only  one  delay  is  specified  , this  value  is  used  for  all  transitions.

->if  two  delays  specified, they  refer  to  the  rise  and fall delay values. The turn-off  delay

Is the minimum of  the  two delays.

->if  all  3  delays  are  specified, they refer  to rise, fall and turn-off delay values.

Eg :   and   #(5)  a1 (out,i1,i2);   //delay  of   5 for all transitions

          and   #(4,6)  a2 (out,i1,i2);  //rise=4,fall=6

          bufif0  #(3,4,5)  b1(out,in,control);   //rise=3,fall=4,turn-off=5

Min/Typ/Max   Values :

Eg1 :  and  #(4:5:6)   a1(out,i1,i2);

Here  4  is minimum  delay(+min delays)

5 is typical  delay(+ty  delays)

6  is  maximum delay(+max  delays)

Eg2 :

and   #(2:3:4,3:4:5,4:5:6)  a3(out,i1,i2);

           Here  2-rise,3-fall,4-turn off  min delays

           3-rise,4-fall,5-turn off  typdelays

            4-rise,5-fall,6-turn off  maxdelays

Timing  checks : $setup  and   $hold :

->$setup,  $hold,  $width

->all  timing  checks  must  be  inside  ‘specify’  blocks

$setup  task  :

$setup (data_event,reference_event,limit);

Data_event : signal that is monitored for violations

Reference_event :  signal that establishes  a  reference  for  monitoring  the  data_event  signal

Limit  :minimum  time  required  for  setup  of  data  event.

$hold   task :

$hold  (reference_event,data_event,limit);

$width  task :

$width (reference_event,limit);

Reference_event : Edge  triggered  event(edge  transition  of  a  signal)

Limit  :  minimum  width  of  the  pulse