## 27 March 2012

### Verilog HDL: Procedural Continuous Assignments

à starts with a keyword “assign

Characteristics of continuous assignments:
• The left hand side of an assignment must always be a scalar or vector net or a concatenation of scalar and vector nets. It can’t be a scalar or vector register.
• Continuous assignments are always active. The assignement  expression is evaluated  as soon as the one of the right hand side operands changes and the value is assigned to the left hand side net.
• The operands on the right hand side can be registers or nets or functions. Register or nets can be scalar or vectors.
• Delay values can be specified for assignments in terms of time units. Delay values are used to control the time when a  net is assigned the evaluated value. This feature is similar to specifying delays for gates.
• The left hand side of procedural continuous assignments can be only be a ‘register’ or a concatenation register. It can’t a ‘part’ or ‘bit select of a net’ or an ‘array of registers’
• Procedural continuous assignments override the effect of regular procedural assignments.

Eg.:
1.       assign out = i1 & i2; // continuous assign. // ’out’ is net //i1 and i2 are nets.
//continous assign for vector nets
// ‘addr’ is a 16 bit vector net
3.       assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;
//concatenation; left hand side is a concatenation of a scalar net and a vector net.
Implicit Continuous Assignment:
Eg.:
wire out;
assign out = in1 & in2;    //regular continuous assignment
wire out = in1 & in2;        //same effect is achieved by an implicit continuous assignment.

### Net Declaration Delay:

à A delay can be specified as  a net when it is declared without putting a continuous assignment on the net. If the delay is specified on a net ‘out’, then any value change applied to the net ‘out’ is delayed accordingly.
Eg.:
1.       wire #10 out;     // net delay
assign out  = in1 & in2;
2.       wire out ;
assign #10 out = in1 & in2;            // same effect as the above example

### Structured  Procedures :-

• The  statements  always  and  initial   can’t  be  nested.
• The  ‘initial’  blocks  are  typically  used  for  initialization, monitoring, waveforms  and other  processes that must be  executed  only  once  during  the entire  simulation  run.

Eg :-
module  stimulus;
reg  x, y,a,b,m;
initial
M=1’b0;   //single  statement;  does  not  need  to  be  grouped
initial
begin
#5    a=1’b1;   //multiple  statements;
#25   b=1’b0;    //need  to  be  grouped
end
initial
begin
#10   x=1’b0;
#25   y=1’b1;
end
initial
#50    \$finish;
endmodule

In  this  example,  the  3  initial  statements  start  to  execute  in  parallel  at  time  0.  If  a  delay # is seen before  a  statement,  the statement  is  executed  <delay>  time  units  after  the  current simulation time.  Thus  the  execution  sequence  of  the  statements  inside  the ‘initial’  blocks  will be as  follows :
Time          statements  executed
0            ---à m=1’b0;
5            ---à a=1’b1;
10          ---à x=1’b0;
30          ---à b=1’b0;
35          ---à y=1’b1;
50          ---à \$finish;

### Always  Statement :-

-the  always  statement starts at  time  zero  and  executes  the executes in the ‘always’ block continuously in a looping fashion.
Eg :-  module  clock_gen(output   reg  clock);
initial
Clock=1’b0;                          //initialize  clock at time zero
always
#10  clock=~clock;            //(time  period=20)
initial
#1000    \$finish;
endmodule