31 March 2012

Verilog HDL: Procedural Timing Controls

Procedural Timing   Controls
·         3  methods :   
o   Delay-based  timing  control
o   Event-based  timing  control
o   Level-sensitive  timing  control

28 March 2012

Verilog HDL: Procedural Assignments

Procedural  Assignments :-
This  update  values  of  reg, integer,real or time variables.  The  value  placed  on  a  variable  will remain unchanged  until another  procedural   assignment  updates  the  variable  with  a  different  value.
The  lefthand  side  of  a  procedural  assignment  <lvalue>   can  be  one  of  the  following :
*      reg, integer,real or time  register  variable  or  a memory  element
*      bit  select  of  those  variables (eg : addr[0])
*      part  select  of  those  variables (eg :  addr[31:16])
*      concatenation  of  any  of  the  above

27 March 2012

Verilog HDL: Procedural Continuous Assignments

à starts with a keyword “assign

Characteristics of continuous assignments:
  • The left hand side of an assignment must always be a scalar or vector net or a concatenation of scalar and vector nets. It can’t be a scalar or vector register.
  • Continuous assignments are always active. The assignement  expression is evaluated  as soon as the one of the right hand side operands changes and the value is assigned to the left hand side net.

Verilog HDL: Hardware Description Using Basic Logic Gates

There are 14 logic gates and 12 switches predefined in the Verilog HDL to provide the gate- and switchlevel modeling facility.
  • Supports basic logic gates as oredefined primitives.
  • and, or, nand, nor, xor, xnor: These gates can have multiple inputs and 1 output.