25 June 2012

RTL Coding for Logic Synthesis

1.1. Synthesizable and Non-Synthesizable Verilog constructs

Identifiers, escaped identifiers, Sized constants (b, o, d, h), Unsized constants (2'b11, 3'07, 32'd123, 8'hff), Signed constants (s) 3'bs101, module, endmodule, macromodule, ANSI-style module, task, and function port lists
system tasks, real constants
Data types
wire, wand, wor, tri, triand, trior, supply0, supply1, trireg (treated as wire), reg, integer, parameter, input, output, inout, memory(reg [7:0] x [3:0];), N-dimensional arrays,
real, time, event, tri0, tri1
Module instances
Connect port by name, order, Override parameter by order, Override parameter by name, Constants connected to ports, Unconnected ports, Expressions connected to ports,
Delay on built-in gates
Generate statements
if,case,for generate, concurrent begin end blocks, genvar,

and, or, nand, nor, xor, xnor,not, notif0, notif1, buf, bufif0, bufif1, tran,
User defined primitives
(UDPs), table, pullup, pulldown, pmos, nmos, cmos, rpmos, rnmos,
rcmos, tranif0, tranif1, rtran, rtranif0,
Operators and
+, - (binary and unary)

Bitwise operations
&, |, ^, ~^, ^~

Reduction operations
&, |, ^, ~&, ~|, ~^, ^~, !, &&, || , ==, !=, <, <=, >, >=, <<, >>, <<< >>>, {}, {n{}}, ?:, function call
===, !==
Event control
event or, @ (partial), event or using comma syntax, posedge, negedge (partial),
Event trigger (->), delay and wait (#)
Bit and part selects
Bit select, Bit select of array element, Constant part select, Variable part select ( +:, -:), Variable bit-select on left side of an assignment

Continuous assignments
net and wire declaration, assign
Using delay
Procedural blocks
always (exactly one @ required),
Procedural statements
;, begin-end, if-else, repeat, case, casex, casez, default, for-while-forever-disable(partial),
fork, join
Procedural assignments
blocking (=), non-blocking (<=)
force, release
Functions and tasks
Functions, tasks

Compiler directives
`define, `undef, `resetall, `ifndef, `elsif, `line, `ifdef, `else, `endif, `include

24 June 2012

Verilog HDL: Test Bench for 4 bit Counter

Test Bench for 4 bit Counter:
module tb_4bitcounter
reg tclk,trst;
wire [3:0]tq;
counter_4bit C1(.tq(q), .tclk(clk), .trst(rst)); instantiate counter to be tested.
#0 trst=1’b0; //tclk=1’b?;
#5 trst=1’b1; //tclk=1’b1;
#100 trst=1’b1; //tclk=1’b0;

Verilog HDL: Test Bench for 4-Bit Adder

Test Bench for 4-Bit Adder:

Verilog HDL: Test Bench

Test Bench
Using Verilog we can write a test bench to apply stimulus to the design and verify the results of the design. Up-front verification becomes very important as design size increases in size and complexity. This ensures simulation results matches with post synthesis results. A test bench can have two parts, the one generates input signals for the model to be tested while the other part checks the output signals from the design under test.
assign à assign values to registers, wires ; synthesizable and hence used in designs.
force , release: assign and deassign values to wire, reg within procedural block; used in verification

Verilog HDL: User-Defined Primitives(UDP)

User-Defined  Primitives(UDP) :
  • One of the advanced concepts in verilog
  • non synthesizable
  • single output many iput
  • consume very less memory
  • I/Os must be scalar (i.e. bit)
  • ‘z’ value is not supported.
primitive myprimitive(c,a,b)
input a,b;
output c;
0 0:0
0 1:0
1 0:0
1 1:0

Verilog HDL: Switch-level Modeling

Mos  switch  keywords :

Verilog HDL: Timing and Delays In Verilog

Timing  and  Delays In Verilog:
Path  Delay  Modeling :-
Specify  Blocks :
->a  delay  between  a source  (input  or  inout)  pin  and  a  destination (output  or  inout)  pin   of  a  module  is  called  a   module path delay
->keywords for path delay : ‘specify’,’endspecify’

Eg :
module  m(out,a,b,c,d) ;
output  out;
input  a,b,c,d;
wire  e,f;
specify       //specify  block with path  delay  statements
         (a => out) = 9;  //for  full connection : (a,b*>out) = 9;
         (b=> out) = 9; 
         (c => out) = 11;  //for  full connection : (c,d*>out) = 11;

         (d => out) = 11; 
and a1(e,a,b);
and a2(f,c,d);
and a3(out,e,f);

Note :
Specify block  is  a  separate  block  in  the  module  and  does  not  appear  under  any  other  block, such  as  initial  or  always.
“specparam”  à  special  parameter  declaration  for  use inside  a specify  block ;  same  as  ‘parameter’   but  only  within  ‘specify’  block.

Rise, fall  and turn off delays :-
->if  only  one  delay  is  specified  , this  value  is  used  for  all  transitions.
->if  two  delays  specified, they  refer  to  the  rise  and fall delay values. The turn-off  delay
Is the minimum of  the  two delays.
->if  all  3  delays  are  specified, they refer  to rise, fall and turn-off delay values.
Eg :   and   #(5)  a1 (out,i1,i2);   //delay  of   5 for all transitions
          and   #(4,6)  a2 (out,i1,i2);  //rise=4,fall=6
          bufif0  #(3,4,5)  b1(out,in,control);   //rise=3,fall=4,turn-off=5

Min/Typ/Max   Values :
Eg1 :  and  #(4:5:6)   a1(out,i1,i2);
Here  4  is minimum  delay(+min delays)
5 is typical  delay(+ty  delays)
6  is  maximum delay(+max  delays)

Eg2 :
and   #(2:3:4,3:4:5,4:5:6)  a3(out,i1,i2);
           Here  2-rise,3-fall,4-turn off  min delays
           3-rise,4-fall,5-turn off  typdelays
            4-rise,5-fall,6-turn off  maxdelays

Timing  checks : $setup  and   $hold :
->$setup,  $hold,  $width
->all  timing  checks  must  be  inside  ‘specify’  blocks
$setup  task  :
$setup (data_event,reference_event,limit);
Data_event : signal that is monitored for violations
Reference_event :  signal that establishes  a  reference  for  monitoring  the  data_event  signal
Limit  :minimum  time  required  for  setup  of  data  event.

$hold   task :
$hold  (reference_event,data_event,limit);

$width  task :
$width (reference_event,limit);
Reference_event : Edge  triggered  event(edge  transition  of  a  signal)
Limit  :  minimum  width  of  the  pulse

Verilog HDL: System Tasks, File Related Operations, Compiler Directives

System  Tasks:
->all  system  tasks  appear  in  the  form  $
->operations   such  as  displaying  on  the  screen,  monitoring  values  of  nets,  stopping,  and  finishing  are  done  by  system tasks.
$display :  system  task  for  displaying  values  of  variables  or  strings   or   expressions very much   similar to  “printf”  in  C
Eg:  $display (p1,p2,p3,………pn);     where  p1,p2,p3  etc.  can  be  quoted  strings or variables or  expressions.

Verilog HDL: Usefull Modelling Techniques

Overriding parameters:
 two ways:
à defparam statement
à module_instance parameter value assignments
defparam statement
module hello_world;
parameter id_num =0 ; //define module id=0
        $display (“…….”);

Verilog HDL: Functions And Tasks

Differences :-
 Functions :-
->can  enable  another  function  but  not  another task.
à function always executes in 0 simulation time.
à functions must not contain any delay, event or timing control statements.
-> functions must have atleast one input argument. They can have more than one input.
à functions always returns a single value. They can’t have output or input arguments.
à Delays are not allowed inside function (i.e. @,#,wait).
à Function return only one value.
àwhile’ and ‘forever’ in function are not supported by synthesis tools.
àrepeat’ is supported by some synthesis tools.
àNo procedural blocks like ‘initial’, ‘always’ inside function allowed.
àNo wire in function.
àFunction can call another function but not another task.

Verilog HDL: Behavioural Modeling: 8-Bit Ring Counter, 8-Bit Adder

8-Bit Ring Counter

Use concatenation operator:
for n bit, xn={x[n-1:0],1’b0}
always @ (posedge reset or posedge clk)
if (reset == 1’b1)
count = 8’b0000_0001;
else if (enable==1’b1)
count={count[6:0],count[7]};     //shift using concatenation operator

Verilog HDL: Behavioural Description of ALU

Arithmatic: +, -, *, /
s2            s1            s0            Operation
0              0             0              +
0              0             1             -
0              1             0             *
0              1             1             /
1              0             0             AND
1              0             1             OR
1              1             0             NOT
1              1             1             XOR
always @(ctrl & a & b)
case (ctrl)
default:out=8’b0; //default value =0;
Case statement execution is faster than if statement . There are several other advantages of using case statements in RTL coding from the ASIC synthesis point of view.

Verilog HDL: Behavioural Modeling

For complex designs, when algorithms are known.
Behavioural Modeling:
always @ (a,b,sel)
always à this block is called structural statement; like cyclic/repetitive behaviour.
@ à event timing control
(a,b,sel) à sensitive list
posedge à +ve edge
negedge à -ve edge
initial à like one shot behaviour/ initialisation purpose; non synthesizable
Sensitivity list should contain all the list of inputs in the combinational circuit. For sequential circuits it is not mandatory. In combinational circuit a missed sensitivity list may violate the functionality of the simulation. But synthesis may be realised properly. Hence we may face simulation and synthesis mismatch.
D-Flip Flop: