17 February 2008

Overview of VLSI Fabrication Facility

Nano fabrication facilities are inevitable for the mass production of integrated circuits. Manufacturing nano range of patterns requires complex process steps to be followed in ultra clean environment. Huge amount of capital in terms of both money and intellectual are necessary to setup a manufacturing facility. As feature size reduces from one node to another smaller node, the installed fabrication equipments may not be compatible to the new node. Thus life time of the fabrication plant is limited by the life time of the node technology. To reduce the cost and to improve the overall throughput in a lesser time, careful design of fabrication facility is important. As and when technology advances the design should provide maximum opportunity to expand to a newer node with less reinvestment.

CMOS process technology

There is not much change in the basic technology used for semiconductor device manufacturing process for last 3 decades. Significant improvements have been made to different processing steps like depositing, etching, diffusing and patterning. Present day technology uses wafers having thickness upto 750 micron. Top surface layer thickness has reduced to 1 micron.

In CMOS technology both nMOS and pMOS transistors are fabricated side by side on the same substrate. Multiple levels of metal and planarization is used in this process. Chip crossection is dominated by interconnection layer. CMOS process technology has advantages of low DC power consumption, high performance and flexible design options. The main technologies to do the fabrication of IC are p-well, n-well, twin tub and Silicon On Insulator (SOI) CMOS process.

In p-well process the substrate is N-type. N channel device is formed into the p-well. The p channel device is directly constructed on the substrate itself. For n-well it is reverse. In twin tub or twin well process both n-well and p-well are fabricated on single N-type substrate. It is possible to tune independently threshold voltage, body effect and the channel transconductance of both P and N type transistors using this process. With n+ or p+ as starting material , lightly doped epitaxial layer is formed on this layer n-well and p-well are formed. Unbalanced drain parasitics are observed in p and n well CMOS process. Twin tub process avoids this problem.

Silicon On Insulator (SOI) process technology makes it possible to fabricate completely isolated pMOS and nMOS transitors side by side. Advantages of SOI process over other CMOS technologies are avoidance of latch up problem, low parasitic capacitances, higher integration density and higher speed.

Process plan

The overall view of the complete CMOS process flow for the fabrication of integrated circuit is briefly explained below.

  • Crystal growth and wafer slicing process:

Step1: obtaining the sand: sand with very good form of clean silicon is used to grow the wafer.

Step2: preparing the molten silicon bath: the sand(SiO2) is heated just above its melting point temperature of 1600ÂșC.

Step3: making the ingot: a seed containing desired crystal orientation is placed onto the molten sand bath. This crystal is slowly pulled out(1mm/minute). Czochralski(CZ) method is used for this process. The resultant pure silicon is called an ingot.

Step 4: preparing the wafers: with a diamond saw ingot is sliced into very thin wafers.

  • Thickness sorting: Sliced wafers are sorted on an automated basis into bathes of uniform thickness.
  • Lapping and etching: Cracked or damaged surface of the silicon wafer due to slicing is removed by lapping. Crystal damages are removed by etching process.
  • Thickness sorting and flatness checking: Once again wafers are sorted acording to their thickness.
  • Polishing process: This process can be either mechanical or chemical or both. Here uneven surface left by lapping and etching processes are smoothened.

Final dimensions and electrical properties qualification: the wafers undergo final test to satisfy customer requirement of flatness , thickness, resistivity and type.

Fabrication:

The prepared wafers are exposed to multiple levels of photolithography process. Each step is repeated for each mask. Mask defines the different layers of the integrated circuit pattern which are designed using CAD tools.

First ixide(SiO2) layer is formed on the wafer.

  • Photolithography: Photoresist coating is applied on the surface of wafer. Wafer is aligned with mask and light source. In the transparent areas of mask light passes through and exposes the photoresist.
  • Direct wafer stepping: In this method mask is kept away from the wafer. With the help of series of optics image is placed on to the wafer. This technique allows larger mask size than the final pattern. Exposed regions of photoresist becomes hard.
  • Etching the wafer surface: This process removes unwanted material from the wafer. There are two main methods of etching: wet etching and dry etching.
  • Wet etching: Chemicals are used for wet etching. Number of wafers are dipped in concentrated acid and exposed areas of wafers are etched away.
  • Dry etching: Gas is used instead of chemical etchants.
  • Plasma etching: An intense electric field is applied to generate the plasma state of gaseous matter. Gases used are very reactive in plasma state. This provides effective etching of exposed surface.
  • Reactive ion etching and ion milling are the other two techniques used for etching.

Implant/masking: diffusion and ion implant:

  • Diffusion: First photoresist is coated and patterning is done using photolithography process. Then wafer is kept in a furnace with a flow of gas running over the wafers. Dopants are slowly diffused.
  • Ion implantation: Here desired dopant ions are shooted (or implanted) into the wafer. This process can handle single wafer at a time while diffusion chamber can handle many wafers at a time.
  • Drive in: Wafers are heated so that implanted(or diffused) ions are go deeper into the wafer.
  • Annealing: Crystal lattice structure of the wafer is disturbed by the diffusion or ion implantation. To repair this wafer is heated so that crystal structure is repeated itself.

The circuit elements are fabricated with different mask operations. Some of the final masks define interconnections.

A passivation layer is coated to protect the entire wafer from the contamination during assembly. Passivation material is etched from the bonding pads using final mask and passivation etch. Then all ICs are tested for its functionalty and non functional ICs are marked. A diamond saw is used to cut the wafer into indivisual chips.

  • Die attach/wire bond: Die is mounted on to the lead frame. A thin gold wire connects between bonding pad and lead frame.
  • Encapsulation: Lead frames are placed onto the mold plates and heated. Molten plastic material is pressed around each die to form its individual IC package.
  • Lead finish/trim and form: Conductivity of the leads are improved by coating tin or lead solution. Then exact form of the leads as per package requirement is formed step by step.
  • Final testing and shipping: Quality, reliabilty and functionality of the each chip is tested. Product type, date, package code etc are marked on to the IC packages. Individual chips are then put into antistatic tubes for shipping.

Equipments Required

Several equipments are required for the complete wafer processing into a chip. Some of the important machines are listed here.

  • Crystal growers: Single crystal ingots are produced by Czochralski (CZ) method. Resistivity is adjusted using the dopants, such as boron and phosphorus.



CZ grower [3] (click on the figure to enlarge it)
  • Wafer slicing machine: This is used to cut single crystal ingot to wafers.

  • Spinner (Photo resist Coater): A spinner used to apply photoresist to the surface of a silicon wafer. Spin speed and spin time can be adjusted.
  • Wafer Cleaners: The processed wafers are cleaned and inspected to be polished wafers.
  • Wafer shaping machines (Lapping machines): These machines are used to remove surface roughness.

  • Wafer polishing machine: Used to make the wafer surface highly flat.

  • SIMOX implanter: Defects made in the wafer surface are removed by annealing and ion implantation. This machine does this job.
  • Epitaxial furnace: This is shown in the Figure (10). This furnace is used for Chemical Vapor Deposition (CVD) to grow epitaxial layer.
  • Hydrogen annealing furnace: Used to improve the surface crystalline perfection by hydrogen annealing.
  • Aligner: This machine is used to align mask to wafer or wafer to wafer.

Generally these machines have 4 modes of operation: proximity, hard and soft contact, vacuum contact. Machine configuration allows processing of 300 inch wafers.





(click on the figure to enlarge it)
  • Etchers: Anisotropic etchings of nitride, oxide, silicon and polymer layers are possible with this machine.Plasma machines generally use chlorine- and fluorine-based chemistries for etching various Si, polysilicon, nitride, tungsten, tungsten silicide films. These machines have different selectivity options. Laser interferometer is used for etch rate determination and end point detection. Some etchers have four independent process chambers. These etchers are capable of metals, oxides and nitrides, silicon and polysilicon. Wafer size can be up to 300 mm.

  • E-Beam Lithography System: This is Ultra high resolution E-beam lithography system. Ultimate resolution specified to 60 nm with sub-30 nm features possible with this machine. E beam is directly exposed to wafers up to 300 mm diameter.
  • Sputter Coater machines: This is used for depositing a conductive coating for visualizing SEM samples.
  • Ellipsometer: Ellipsometer allows measurement of the thickness and refractive index of very thin transparent films.
  • Surface Profile meter: This instrument is used to measure step heights and roughness of surfaces. It also measures many other surface topography parameters. The measurement technique is either contact or contact less; both are used in the industry. Optical phase shifting interferometry concept is being used in the equipment.
  • Asher: Used to strip the photo resist from the wafer. Plasma of oxygen and nitrogen reacts with the photo resist and burns off the wafer.



(click on the figure to enlarge it)
  • Laser Writer (mask making machine): This machine accepts GDS II format input file and generate mask patterns.
  • Film Thickness Measurement: This system uses non-contact, spectro-reflectometry (measurement of the intensity of reflective light as a function of incident wavelength) to determine the thickness of transparent films on substrates, such as silicon, that are reflective in the visible range.
  • Resistivity Measurement: This resistive measurement instrument collects and analyzes sheet resistance data on various conductive layers such as implants, diffusions, epi, metals and bulk substrates.
  • Wafer Dicing saw: This machine is used to cut the wafers into individual die. It utilizes rotary blade. Some wafer cutting machine diamond saw.
  • Field Emission Scanning Electron Microscope: This is high resolution imaging instrument. This instrument has a resolution of 5nm and less.
  • Film Stress Tester: This equipment measures the stress induced by the deposited films on a substrate. Deflection of a scanning laser beam is used for the measurement. With and without the deposited film change in the curvature of the wafer is measured.

Developer: Exposed photo resist wafers are developed with the help of this machine. This machine has facility for dispensing developer and post bake oven station. Number wafers and size of the wafer which can be processed is machine specific.

Flow area required to install and use the equipments

There is distinct difference in the requirements of the laboratories and the clean room. Significant differences can be found in the requirements of in these two areas.

Total area required for the complete fabrication plant along with its all support facilities is likely to be 1,00,000 sf.( square feet). Building is considered to be of one floor i.e. ground floor. Thus the individual area required for the fabrication plant is approximately as follows: the manufacturing, production and assembly area is around 1,500 sf; the production and lab support areas like service area, maintenance group area, CAD facilities etc cover around 25,000 sf; utility areas such as conference rooms, library, lounge etc cover around 6,000 sf of the fabrication plant; the main laboratory requires an area of around 2,000 sf. Thus the required area for the clean room of class 10 is around 3,000 to 5,000 sf.

All remaining space of clean room quality class 100,1000 and 10,000 including office area, stock room, storage area for gases cover around 10,000 sf. Remaining area is required for loading and unloading duck , DI water plant, cold and chilled water plant, several other gas storage and purifying plants. If clean room of class 10 is having an area around 5,000 sf then the supporting clean room area can be around 6,000sf.

Fabrication plant layout and location of equipments

A general layout of the fabrication plant is shown in the Figure. The layout shows a general distribution of area for different processes and facilities. Fluorescent lighting system is used for the fabrication building. Class 10 clean room is lighted with yellow fluorescent light. Photo resists are less sensitive to the yellow light. All other areas of the building are lighted with fluorescent lamp. Fire protection systems are installed all over the fabrication plant. The layout for the lithography, etching and diffusion operation are kept nearer to each other as these processes are repeated several times. Conference rooms, library and other office rooms are outside the clean room. The clean room quality for these areas can be up to class 10,000. Temperature and humidity are controlled to 73.4F +/- 5.0 F, 50% +/- 10% RH. The clean room maintains at least .05" H2O over atmospheric.

Placement of equipment in the fabrication plant is a very critical issue. Airflow and the ultimate cleanliness capability of the area surrounding the equipment have to be maintained adequately as per the standard requirement of the fabrication plant. For the placement of the equipment several factors have to be considered. Size and the shape of the equipment mainly decide the area requirement of the equipment. In addition to this the other factors to be considered are the access required to operate and service the equipment, the location and number of utility connections to the equipment, and the amount of support equipment located near the equipment and how it connects to the equipment. Equipment locations must satisfy all safety related standards.

Today, bulk head mounting design methodology is used for most of the semiconductor equipments. In this design bulk of the equipment resides in the chase and remaining small portion of the equipment is located in clean room. The preferred method for equipment placement is to keep the equipment face is flush with the clean room wall. This design allows easy air flow, the best possible easy access to the equipment. Utilities are well connected to the system. Highest level of cleanliness can be maintained.



Layout of the fabrication facility [3] (click on the figure to enlarge it)

In addition to the main equipments many supporting equipments are used in the fabrication plant. Location for such support equipments must be carefully planned. It is good practice to keep supporting equipments in chase. If they are kept in clean room they disturb the airflow and also require additional maintenance activities. This eats up clean room floor area.

Airflow requirement has to be considered when equipment can’t be bulkhead mounted. The key in the equipment placement is to ensure that the cleanest air coming from ULPA filters is directed to the critical areas of the equipment.

The floor above the clean room is used for air handlers and heat exchangers. Support equipments such as air compressors, chilled water, vacuum pumps and acid neutralizers are kept away from the clean room. Storing corrosive and toxic gases in clean room is hazardous. Hence they are stored and monitored away from the main laboratory itself. An outdoor area, known as facility area, is utilized for storing the DI water, chilled water, liquid gases and emergency power generators. Support facilities are essential for the smooth clean room operation. Stock room, semi clean laboratory, maintenance work areas and staff offices are located near to the clean room.

Fire suppression systems are installed such that they provide suitable fire protection to the equipment, contribute no contamination to the equipment, and allow proper airflow to the product-wafer areas. Fire extinguishers are located at strategic locations throughout the clean room and other sub laboratory areas. Generally preferred area is the chase. Location of extinguishers should not be in the airflow path leading to product-wafer areas.

Service facilities

Brief explanation of the several service facilities required for the fabrication plant is given below.

  • Emergency gas shutoff systems: This system is a pressurized loop tied to normally closed valves on hazardous gases entering the fabrication plant. The emergency shutoff stations located at different strategic points around the plant.

  • Toxic gas monitoring system: This is either a microprocessor or PLC controlled system. The system monitors the hazardous level of different hazardous gases of type-hydride, oxidizer, mineral acid and pyrolyzer at both sides-source and at the point of use. Inputs of the gas monitoring system are located at the point of use and the exhaust duct immediately upstream from where an emission is most likely to occur. When installing such detection systems specific gravity of the gases has to be taken into consideration.

  • Containment pressure monitoring system: This system mainly checks three important conditions: high pressure, low pressure and zero (atmospheric) pressure. High and low pressure indicates leakage of gases while atmospheric pressure in the gas supply pipe indicates a catastrophic failure of the system.

  • Safety Shower/Eyewash Stations: The place where hazardous liquids are used there safety showers and eyewash stations are required. Locations must be chosen such that an electrical hazard is not created by the discharge of the safety shower. Any electrical outlets in proximity to the shower must be protected by ground-fault circuit interruption.

  • Fire Suppression Systems and extinguishers: Those equipments having combustible material and chemical are equipped with fire suppression and extinguishable systems. The extinguishers used should be compatible with the chemicals used in the system.

  • Particle Filters (HEPA and ULPA): HEPA (High-Efficiency Particulate Air) Filters rated 99.99% are efficient in filtering particles 0.3 microns and larger in diameter. ULPA (Ultra-Low Penetration Air) Filters rated 99.999% can efficiently filter particles of size 0.12 microns in diameter. These filters are available in variety of sizes which are specifically designed and used for clean rooms of class 10 specification. The filtration medium consists of highly efficient micro porous polyurethane mini plates.
  • Air handlers: Air handlers consisting of ULPA and HEPA filters handle recirculation of air in clean room to maintain positive pressure and to provide cooling to support areas and office.
  • Exhaust system: Exhaust systems treat hazardous gases prior to being scrubbed by the fluoride exhaust.
  • High Purity Bulk Gases: Different bulk gases required to the wafer fabrication building. They are: nitrogen, hydrogen and oxygen. Oxygen and nitrogen are required of two different qualities, one is ultra high purity and the other is "house" quality.
  • Chilled water supply system: Water from this system is used for dehumidification on the outside air units.
  • Vacuum pumps: These systems provide necessary vacuum for the machines located at clean room and elsewhere.
  • Air compressors: Air compressors provide 60 deg C dew point air to the Wafer building.

References

[1] Silicon Wafer Processing, Dr. Seth P. Bates, 2000, http://iisme.org/etp/Silicon_Wafer_Processing.pdf
[2] www.sumcosi.com/english
[3] http://snf.stanford.edu
[4] http://www.teertech.com/teer.doc.htm

16 February 2008

Physical Design Questions and Answers

  • I am getting several emails requesting answers to the questions posted in this blog. But it is very difficult to provide detailed answer to all questions in my available spare time. Hence i decided to give "short and sweet" one line answers to the questions so that readers can immediately benefited. Detailed answers will be posted in later stage.I have given answers to some of the physical design questions here. Enjoy !


What parameters (or aspects) differentiate Chip Design and Block level design?
  • Chip design has I/O pads; block design has pins.
  • Chip design uses all metal layes available; block design may not use all metal layers.
  • Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.
  • Chip design requires several packaging; block design ends in a macro.

How do you place macros in a full chip design?
  • First check flylines i.e. check net connections from macro to macro and macro to standard cells.
  • If there is more connection from macro to macro place those macros nearer to each other preferably nearer to core boundaries.
  • If input pin is connected to macro better to place nearer to that pin or pad.
  • If macro has more connection to standard cells spread the macros inside core.
  • Avoid criscross placement of macros.
  • Use soft or hard blockages to guide placement engine.

Differentiate between a Hierarchical Design and flat design?
  • Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no subblocks and it has only leaf cells.
  • Hierarchical design takes more run time; Flattened design takes less run time.

Which is more complicated when u have a 48 MHz and 500 MHz clock design?
  • 500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz design.

Name few tools which you used for physical verification?
  • Herculis from Synopsys, Caliber from Mentor Graphics.

What are the input files will you give for primetime correlation?
  • Netlist, Technology library, Constraints, SPEF or SDF file.


If the routing congestion exists between two macros, then what will you do?
  • Provide soft or hard blockage

How will you decide the die size?
  • By checking the total area of the design you can decide die size.

If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
  • Poly

If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
  • Because top two metal layers are required for global routing in chip design. If top metal layers are also used in block level it will create routing blockage.

In your project what is die size, number of metal layers, technology, foundry, number of clocks?
  • Die size: tell in mm eg. 1mm x 1mm ; remeber 1mm=1000micron which is a big size !!
  • Metal layers: See your tech file. generally for 90nm it is 7 to 9.
  • Technology: Again look into tech files.
  • Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc
  • Clocks: Look into your design and SDC file !

How many macros in your design?
  • You know it well as you have designed it ! A SoC (System On Chip) design may have 100 macros also !!!!

What is each macro size and number of standard cell count?
  • Depends on your design.

What are the input needs for your design?
  • For synthesis: RTL, Technology library, Standard cell library, Constraints
  • For Physical design: Netlist, Technology library, Constraints, Standard cell library

What is SDC constraint file contains?
  • Clock definitions
  • Timing exception-multicycle path, false path
  • Input and Output delays

How did you do power planning?
How to calculate core ring width, macro ring width and strap or trunk width?
How to find number of power pad and IO power pads?
How the width of metal and number of straps calculated for power and ground?
  • Get the total core power consumption; get the metal layer current density value from the tech file; Divide total power by number sides of the chip; Divide the obtained value from the current density to get core power ring width. Then calculate number of straps using some more equations. Will be explained in detail later.
How to find total chip power?
  • Total chip power=standard cell power consumption,Macro power consumption pad power consumption.

What are the problems faced related to timing?
  • Prelayout: Setup, Max transition, max capacitance
  • Post layout: Hold

How did you resolve the setup and hold problem?
  • Setup: upsize the cells
  • Hold: insert buffers

In which layer do you prefer for clock routing and why?
  • Next lower layer to the top two metal layers(global routing layers). Because it has less resistance hence less RC delay.

If in your design has reset pin, then it’ll affect input pin or output pin or both?
  • Output pin.

During power analysis, if you are facing IR drop problem, then how did you avoid?
  • Increase power metal layer width.
  • Go for higher metal layer.
  • Spread macros or standard cells.
  • Provide more straps.

Define antenna problem and how did you resolve these problem?
  • Increased net length can accumulate more charges while manufacturing of the device due to ionisation process. If this net is connected to gate of the MOSFET it can damage dielectric property of the gate and gate may conduct causing damage to the MOSFET. This is antenna problem.
  • Decrease the length of the net by providing more vias and layer jumping.
  • Insert antenna diode.

How delays vary with different PVT conditions? Show the graph.
  • P increase->dealy increase
  • P decrease->delay decrease

  • V increase->delay decrease
  • V decrease->delay increase

  • T increase->delay increase
  • T decrease->delay decrease

Explain the flow of physical design and inputs and outputs for each step in flow.

What is cell delay and net delay?

  • Gate delay
  • Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma]

  • Gate delay =function of(i/p transition time, Cnet+Cpin).

  • Cell delay is also same as Gate delay.

  • Cell delay

  • For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

  • Intrinsic delay

  • Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

  • It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor.

  • This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

  • Net Delay (or wire delay)

  • The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

  • It is due to the finite resistance and capacitance of the net.It is also known as wire delay.

  • Wire delay =fn(Rnet , Cnet+Cpin)

What are delay models and what is the difference between them?
  • Linear Delay Model (LDM)
  • Non Linear Delay Model (NLDM)

What is wire load model?
  • Wire load model is NLDM which has estimated R and C of the net.

Why higher metal layers are preferred for Vdd and Vss?
  • Because it has less resistance and hence leads to less IR drop.

What is logic optimization and give some methods of logic optimization.
  • Upsizing
  • Downsizing
  • Buffer insertion
  • Buffer relocation
  • Dummy buffer placement

What is the significance of negative slack?
  • negative slack==> there is setup voilation==> deisgn can fail

What is signal integrity? How it affects Timing?
  • IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues.
  • If Idrop is more==>delay increases.
  • crosstalk==>there can be setup as well as hold voilation.

What is IR drop? How to avoid? How it affects timing?
  • There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop.
  • If IR drop is more==>delay increases.

What is EM and it effects?
  • Due to high current flow in the metal atoms of the metal can displaced from its origial place. When it happens in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro Migration.

  • Affects: Either short or open of the signal line or power line.

What are types of routing?
  • Global Routing
  • Track Assignment
  • Detail Routing

What is latency? Give the types?
  • Source Latency
  • It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".

  • Delay from clock source to beginning of clock tree (i.e. clock definition point).

  • The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

  • Network latency

  • It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".

  • The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

What is track assignment?
  • Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets.

What is congestion?
  • If the number of routing tracks available for routing is less than the required tracks then it is known as congestion.

Whether congestion is related to placement or routing?
  • Routing

What are clock trees?
  • Distribution of clock from the clock source to the sync pin of the registers.

What are clock tree types?
  • H tree, Balanced tree, X tree, Clustering tree, Fish bone

What is cloning and buffering?
  • Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.
  • Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy.