- When setup or hold window is violated in an flip flop then signal attains a unpredictable value or state known as metastability.
What is MTBF? What it signifies?
- MTBF-Mean Time Before Failure
- Average time to next failure
How chance of metastable state failure can be reduced?
- Lowering clock frequency
- Lowering data speed
- Using faster flip flop
What are the advantages of using synchronous reset ?
- No metastability problem with synchronous reset (provided recovery and removal time for reset is taken care).
- Simulation of synchronous reset is easy.
What are the disadvantages of using synchronous reset ?
- Synchronous reset is slow.
- Implementation of synchronous reset requires more number of gates compared to asynchronous reset design.
- An active clock is essential for a synchronous reset design. Hence you can expect more power consumption.
What are the advantages of using asynchronous reset ?
- Implementation of asynchronous reset requires less number of gates compared to synchronous reset design.
- Asynchronous reset is fast.
- Clocking scheme is not necessary for an asynchronous design. Hence design consumes less power. Asynchronous design style is also one of the latest design options to achieve low power. Design community is scrathing their head over asynchronous design possibilities.
What are the disadvantages of using asynchronous reset ?
- Metastability problems are main concerns of asynchronous reset scheme (design).
- Static timing analysis and DFT becomes difficult due to asynchronous reset.
What are the 3 fundamental operating conditions that determine the delay characteristics of gate?
How operating conditions affect gate delay?
- Click here to read more.
Is verilog/VHDL is a concurrent or sequential language?
- Verilog and VHDL both are concurrent languages.
- Any hardware descriptive language is concurrent in nature.
In a system with insufficient hold time, will slowing down the clock frequency help?
- Making data path slower can help hold time but it may result in setup violation.
In a system with insufficient setup time, will slowing down the clock frequency help?
- Making data path faster can also help setup time but it may result in hold violation.