27 September 2007

Power Gating

Power gating is the technique wherein circuit blocks that are not in
use are temporarily turned off to reduce the overall leakage power of
the chip. This temporary shutdown time can also called as "low power
mode" or "inactive mode". When circuit blocks are required for
operation once again they are activated to "active mode". These two
modes are switched at the appropriate time and in the suitable manner
to maximize power performance while minimizing impact to performance.
Thus goal of power gating is to minimize leakage power by temporarily
cutting power off to selective blocks that are not required in that
mode.


Power gating affects design architecture more compared to the clock
gating
. It increases time delays as power gated modes have to be
safely entered and exited. The possible amount of leakage power saving
in such low power mode and the energy dissipation to enter and exit
such mode introduces some architectural trade-offs.


How to shut down the blocks? It can be accomplished either by software
or hardware. Driver software can schedule the power down operations.
Hardware timers can be utilized. A dedicated power management
controller is the other option.


An externally switched power supply is very basic form of power gating
to achieve long term leakage power reduction. To shutoff the block for
small interval of time internal power gating is suitable. CMOS
switches that provide power to the circuitry are controlled by power
gating controllers.


Output of the power gated block discharge slowly. Hence output voltage
levels spend more time in threshold voltage level. This can lead to
larger short circuit current.


Isolation Cells

Isolation cells are used to prevent short circuit current. As the name
indicates these cells isolate power gated block from the normally on
block. Isolation cells are specially designed for low short circuit
current when input is at threshold voltage level. Isolation control
signals are provided by power gating controller.


Retention Registers

Retention registers are special low leakage flip-flops used to hold
the the data of main register of the power gated block. Thus internal
state of the block during power down mode can be retained and loaded
back to it when the block is reactivated. retention registers are
always powered up. The retention strategy is design dependent. During
the power gating data can be retained and transfered back to block when
power gating is withdrawn. Power gating controller controls the
retention mechanism such as when to save the current contents of the
power gating block and when to restore it back.

Related Articles

Low Power Techniques: Clock Gating

Low Power Techniques: Multi Voltage

Low Power Techniques: Multiple Threshold Cell Libraries


Reference


Michael Keating, David Flynn, Robert Aitken, Alan Gibbons, Kaijian
Shi,"Low Power Methodology Manual For System on Chip Design",
Electronic Edition,Springer, 2007. www.lpmm-book.org

26 September 2007

Limits of Dynamic Voltage and Frequency Scaling (DVFS)

Dynamic voltage and frequency scaling (DVFS) is very popular low power
technique. But larger voltage ranges does not improve power
efficiency. Authors in [1] showed that for sub threshold supply
voltages, leakage energy becomes dominant, making "just in time
completion" energy inefficient. They also showed that extending
voltage range below half Vdd will improve the energy efficiency for
most processor designs while extending this range to sub threshold
operations is beneficial only for specific applications. One of the
important points to be noted from their study is DVFS in sub threshold
voltage range is never energy efficient.


We know that supply voltage can be reduced if frequency of operation
is reduced. If reduction in supply voltage is quadratic then
approximately cubic reduction of power consumption can be achieved.
However, it should be noted that frequency reduction slows the
operation.


The above mentioned relation between energy and voltage is not always
true. The authors in [1] showed that quadratic relationship between
energy and Vdd deviates as Vdd is scaled down into the sub threshold
voltage level. Sub threshold leakage power increases exponentially
with the supply voltage. Since in sub threshold operation the on
current takes the form of sub threshold current delay increases
exponentially with voltage scaling. At very low voltages dynamic power
reduces quadratically. But the leakage energy increases with supply
voltage reduction since leakage energy is linear with the circuit
delay. Hence dynamic and leakage power becomes comparable in
sub threshold voltage region.


Related Articles

Multiple Voltage ASIC/SoC Designs: Classification


Multiple Voltage Design Challenges

Multiple Voltage Designs: Timing Issues


=============================================================================
Reference:
[1]Bo Zhai, David Blaauw, Dennis Sylvester, Krisztian Flaunter,
"Theoretical and Practical Limits of Dynamic Voltage Scaling", DAC
2004, June 7-11, 2004, San Diago, California, USA.

Multi Voltage Designs: Power Planning Issues

Efficient power planning is one of the key concerns of modern SoC
designs. In multi voltage designs providing power to the different
power domains is challenging. Every power domain requires independent
local power supply and grid structure and some designs may even have a
separate power pad. Separate power pad is possible in flip-chip
designs and power pad can be taken out near from the power domain.
Other chips have to take out the power pads from the periphery which
can put limit to the number of power domains.


Local on chip voltage regulation is good idea to provide multiple
voltages to different circuits. Unfortunately most of the digital CMOS
technologies are not suitable for the implementation of either
switched mode of operation or linear voltage regulations.


Separate power rail structure is required for each power domain. These
additional power rails introduce different levels of IR drop putting
limit to the achievable power efficiency.


Related Articles

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Design Challenges

Multiple Voltage Designs: Timing Issues


Variable Threshold CMOS (VTCMOS) Circuits

One of the efficient methods to reduce power consumption is to use low
supply voltage and low
threshold voltage without loosing speed performance. But increase in
the lower threshold voltage devices leads to increased subthreshold
leakage and hence more standby power consumption.

Variable Threshold CMOS (VTCMOS) devices are one solution to this
problem. In VTCMOS technique threshold voltage of the low threshold
devices are varied by applying variable substrate bias voltage from a
control circuitry.


VTCMOS technique is very effective technique to reduce the power
consumption with some drawbacks related to manufacturing of these
devices. VTCMOS requires either twin well or triple well technology to
achieve different substrate bias voltage levels at different parts of
the IC. The area overhead of the substrate bias control circuitry is
negligible.

Multi Voltage Designs: Timing Issues

Clock

Clock Tree Synthesis (CTS) tools should be aware of different power
domains and understand the level shifters to insert them in
appropriate places. Clock tree is routed through level shifters to
reach different power domains. Simultaneous timing analysis and
optimization is necessary for multiple voltage domains. Thus CTS
becomes more complex in multi voltage designs.

Static Timing Analysis (STA)


Timing analysis for single voltage design is easy.When it comes to
static voltage scaling it becomes little tougher job as analysis has
to be carried out for different voltages.This methodology requires
libraries which are characterized for different voltages used.


Multi level and dynamic voltage scaling pose a greater challenge. For
each supply voltage level or operating point constraints are
specified. There can be different operating modes for different
voltages. Constraints need not be same for all modes and voltages. The
performance target for each mode can vary. EDA tool should be capable
of handling all these situations simultaneously to carry out timing
analysis. Different constraints at different modes and voltages have
to be satisfied.


Related Articles

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Design Challenges

Multiple Voltage Designs: Power Planning Issues



Multiple Voltage Design Challenges

Level Shifters

Signals crossing from one voltage domain to another voltage domain has
to be interfaced through the level shifter buffers which appropriately
shifts the signal levels. Design of suitable level shifter is a
challenging job.


Timing Analysis

Timing analysis of the given design becomes simpler with the single
voltage as it can be performed for single performance point based on
the characterized libraries. Tools can optimize the design for worst
case PVT (Process, Voltage, temperature) conditions.


This is not the case with multi voltage designs. Libraries should be
characterized for different voltage levels that are used in the
design. EDA tool has to optimize individual blocks or subsystems and
also multiple voltage domains. This analysis becomes complex for
larger ASIC/SoC.


Floorplanning and Power Planning

Multiple power domain demands multiple power grid structure and a
suitable power distribution among them. For a larger ASIC/SoC more
careful floorplanning and power planning is essential


The speed in which different power domains switch on or off also
important. A low voltage power domain may activate early compared to
the the high voltage domain. Multi voltage designs pose additional
board level complexities. Separate power supply may necessary to
provide different power levels.


Related Articles

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Designs: Timing Issues

Multiple Voltage Designs: Power Planning Issues



Multiple Voltage ASIC/SoC Designs: Classification

Multi voltage (Vdd) design strategies can be broadly classified as follows:

1) Static Voltage Scaling (SVS)

Different but fixed voltage is applied to different blocks or
subsystems of the SoC design.


2) Multi-level Voltage Scaling (MVS)

The block or subsystem of the ASIC or SoC design is switched between
two or more voltage levels. But for different operating modes limited
number of discrete voltage levels are supported.


3) Dynamic Voltage and Frequency Scaling (DVFS)

Voltage as well as frequency are dynamically varied as per the
different working modes of the design so as to achieve power
efficiency. When high speed of operation is required voltage is
lowered to attain higher speed of operation with the penalty of
increased power consumption.


4) Adaptive voltage Scaling (AVS)

Here voltage is controlled using a control loop. This is an extension of DVFS.


Related Articles

Multiple Voltage Designs: Timing Issues

Multiple Voltage Designs: Power Planning Issues

Low Power Techniques: Multi Voltage (Vdd)

25 September 2007

Multiple Threshold (Multi Vt) Cell Libraries

With the technologies shrinking to 90nm, 30nm and below one of the
common ways to reduce leakage power is to use multiple Vt libraries.
Subthreshold leakage varies exponentially with the Vt comparated to
the weaker dependance of delay over Vt.


Libraries are offered in different versions each consisting of
standard Vt cells, low Vt cells and high Vt cells independant of each
other. Power and timing is optimized based on these libraries and they
offer good flexibility and opportunity to logic and physical synthesis
tool for optimization process.


Dual Vt synthesis flow has become quite common in 130nm and below
tehnology nodes. In this flow initial synthesis is carried out
targeting primary library which may be a low Vt or high Vt or normal
Vt library, and the second iteraton of synthesis and optimization is
performed based on secondary libraries which are also libraries
consistitng of multiple threshold cells.


Which library has to be used as primary library ?


This depends on the optimization target as per the design requirement.
In general, if optimization target is power performance, first
syntheize the design using the high Vt cell library which achieves
lowest leakage power. In the next iteration of optimization cells in
the critical path has to be replaced by low Vt cells which are faster.
If the optimization target is to meet timing then first use low Vt
cell library to achieve timing and then optimize leakage power using
high Vt cells.

24 September 2007

Low Power Techniques: Multi Voltage (Vdd)

Dynamic power is directly proportional to power supply. Hence
naturally reducing power significantly improves the power
performance.At the same time gate delay increases due to the decreased
threshold voltage.


High voltage can be applied to the timing critical path and rest of
the chip runs in lower voltage. Overall system performance is
maintained.


Different blocks having different voltage supplies can be integrated
in SoC. This increases power planning complexity in terms of laying
down the power rails and power grid structure. Level shifters are
necessary to interface between different blocks.


Related Articles

Low Power Techniques: Clock Gating

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Designs: Timing Issues

Multiple Voltage Designs: Power Planning Issues



Low Power Techniques: Clock Gating

Clock buffers consume more than 50 % of dynamic power. Hence it is
good design idea to turn off the clock when it is not needed.Automatic
clock gating is supported by modern EDA tools. They identify the
circuits where clock gating can be inserted.

Specific clock gating cells are required in library to be utilized by
the synthesis tools. Availability of clock gating cells and automatic
insertion by the EDA tools makes it simpler method of low power
technique. Advantage of this method is that clock gating does not
require modifications to RTL description.



Related Articles

Low Power Techniques: Multi Voltage (Vdd)

Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Designs: Timing Issues

Multiple Voltage Designs: Power Planning Issues



18 September 2007

Leakage Power

Leakage Power

The power consumed by the subthreshold currents and by
reverse biased diodes in a CMOS transistor are
considered as leakage power.The leakage power of a
CMOS logic gate does not depend on input transition or
load capacitance abd hence it remains constant for a
logic cell.


Subthreshold Current

The subthreshold current always flow from source to
drain even if the gate to source voltage is lesser
than the threshold voltage of the device. This happens
due to the carier diffusion between the source and
drain regions of the CMOS tranistor in weak inversion.

When gate to source voltage is smaller than but very
close to threshold voltage of the device then
subthreshold current becomes significant.


How to minimize subthreshold leakage?

A increase in the threshold voltage of the device
keeps the Vgs of the NMOS transistor safely below the
Vt,n. This is the case for logic zero input. For the
logic one input increase in the threshold voltage of
the device keeps the Vgs of the PMOS transistor
safely below the Vt,p.

Reverse Biased Diode Current

Parasitic diodes formed between the diffusion region
of the transistor and substrate consume power in the
form of reverse bias current which is drwn from the
power supply.



I inverter when input is high NMOS transistor is ON
and output voltage is discharged to zero. Now between
drain and the n-well a reverse potential difference of
Vdd is established whcih causes diode leakage through
the drain junction.

The n-well region of the PMOS transistor w.r.to.
p-type sustrate is also reverse biased. This also
leads to leakage current at the N-well junction.

The reverse current can be mathematically expressed
as,

Ireverse=A.Js.(exp(q.Vbias/kT)-1)

where,
Vbias-->reverse bias voltage across the junction
Js-->reverse satuartion current density
A-->junction area

14 September 2007

Short circuit power

Short circuit power


Consider an exaple of inverter. During switching both
NMOS and PMOS transistors in the circuit conduct
simultaneously for a short amount of time. This forms
direct current path between the power supply and the
ground. This current has no contribution towards
charging of the output capacitance of the logic gate.

When the input rising voltage exceedds the threshold
voltage of NMOS transistor, it starts conducting.
Similarly untill input voltage reaches Vdd-|Vt,p| PMOS
transistor remains ON. Thus for some time both
transistors are ON. Similar event causes short circuit
current to flow when signal is falling. Short circuit
current terminates when transition is completed.

Assuming symmetric inverter with Kn=Kp=K and
Vt,n=|Vt,p|=Vt and very small capacitive load and both
rise and fall times are same we can write,

Pavg(short circuit)=1/12.k.Tow.fclk.(Vdd-2Vt)3.

Thus short circuit power is directly proportional to
rise time, fall time and k.

Therefore reducing the input transition times will
decrease the short circuit current component. But
propagation delay requirements have to be considered
while doing so.
======================================================
Reference:

Sung Mo Kang and Yusuf Leblebici, CMOS digital
integrated circuits-analysis and design, Tata McGraw
hill, third edition, 2003
======================================================


Dynamic (switching) power

As we seen in earlier blog the average power consumed
by the CMOS circuit can be devided into three
different components[1]. They are:

1)Dynamic (switching)power consumption

2)Short circuit power consumption

3)Static (Leakage) power consumption
==========================================================================

Dynamic (switching) power dissipation

As the name indicates it occurs when signals which
goes through the CMOS circuits change their logic
state. At this moment energy is drawn from the power
supply to charge up the output node
capacitance.Charging up of the output capacitnce
causes transition from 0V to Vdd.Considering an
inverter exaple power drawn from the power supply is
dissipated as heat in pMOS transitor.
On the other hand charge down process causes NMOS
transistor to dissipate heat.

Output capacitance of the CMOS logic gate consists of
below components:

1)Output node capacitance of the logic gate: This is
due to the drain diffusion region.

2)Total interconnect capacitance: This has higher
effect as technology node shrinks.

3)Input node capacitance of the driven gate: This is
due to the gate oxide capacitance.


To find the avearage power energy required to charge
up the output node to Vdd and charge down the total
output load capacitance to ground level is integrated.
Applied input periodic waveform having its period T is
assumed to be having zero rise and fall time. Note
that average power is independent of transistor size
and characteristics.

Internal power

This is the power consumed by the cell when an input
changes, but output does not chnage[2]. In
logic gates not every change of the current running
through an input cell necessarily leads to a change in
the state of the output net. Also internal node
voltage swing can be only Vi which can be smaller than
the full voltage swing of Vdd leading to the partial
voltage swing.

======================================================
How to reduce dynamic power?

1)reduce power supply voltage Vdd
2)reduce voltage swing in all nodes
3)reduce the switching probabilty (transition factor)
4)reduce load capacitance

=======================================================
Reference:

[1] Sung Mo Kang and Yusuf Leblebici, CMOS digital
integrated circuits-analysis and design, Tata McGraw
hill, third edition, 2003
[2]Astro User Guide, Version X-2005.09, September 2005
=======================================================


11 September 2007

Different Types of Power Consumption in CMOS Circuits

Different Types of Power Consumption in CMOS Circuits

The average power consumed by the CMOS circuit can be devided into three
different components[1]. They are:

1)Dynamic (switching)power consumption

2)Short circuit power consumption

3)Static (Leakage) power consumption

Detail discussion on these topics we will see in coming blogs !

=======================================================
Reference:

[1] Sung Mo Kang and Yusuf Leblebici, CMOS digital integrated circuits-analysis and design, Tata McGraw hill, third edition, 2003
=======================================================