09 July 2007

ASIC...some good Q's and A's

Click here to read more VLSI/ASIC/CMOS/Digital design interview questions and answers !

I have put by best effort to give correct answers. If u finds something wrong or answers can be improved please leave a comment or mail me……..enjoy!

1) What are High-Vt and Low-Vt cells?

Ans: Hvt cells are MOS devices with less leakage due to high Vt but they have higher delay than low VT, where as the low Vt cells are devices, which have less delay, but leakage is high. The threshold (t) voltage dictates the transistor switching speed, it matters how much minimum threshold voltage applied can make the transistor switching to active state, which results to how fast we can switch the transistor. Disadvantage is it needs to maintain the transistor in a minimum sub threshold voltage level to make it switch fast so it leads to leakage of current in turn loss of power.


2) What is useful-skew mean?

Ans: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.


3) Draw Vds-Ids curve for an MOSFET. How it varies with

a) Increasing Vgs

b) Velocity saturation

c) Channel length modulation

d) W/L ratio

Ans: I hope u can draw it…. Refer: Kang, pp.109 and other pages.


4) What is body effect? Write mathematical expression? Is it due to parallel or serial connection of MOSFETs?

Ans1: Increase in Vt (threshold voltage), due to increase in Vs (voltage at source), is called as body effect. It is due to serial connection. For math equation refer: Kang, pp.95.

Ans2: In general multiple MOS devices are made on a common substrate. As a result, the substrate voltage of all devices is normally equal. However while connecting the devices serially this may result in an increase in source-to-substrate voltage as we proceed vertically along the series chain (Vsb1=0, Vsb2 0). Which results Vth2>Vth1.


5) What is latch up in CMOS design and ways to prevent it?

Ans1: Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS).

Ans2: Latch-up is a condition in which the parasitic components give rise to the Establishment of low resistance conducting path between VDD and VSS with Disastrous results


6) What is Noise Margin? Relate it with Inverter.



After writing this equations draw inverter characteristics curve and show these points in the input and output axis.


7) What happens to delay if you increase load capacitance?

Delay increases.


8) For CMOS logic, give the various techniques you know to minimize power consumption?

Power dissipation=2fCVDD è minimize the load capacitance C, dc voltage VDD and the operating frequency f.
9) All of us know how an inverter works. What happens when the PMOS and NMOS are interchanged with one another in an inverter?

Ans: O/P will be degraded 1 and degraded 0. (Check with SPICE simulation!)


10) Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits?

1) In digital design, decide the height of standard cells you want to layout. It depends upon how big your transistors will be. Have reasonable width for VDD and GND metal paths. Maintaining uniform Height for all the cell is very important since this will help you use place route tool easily and also incase you want to do manual connection of all the blocks it saves on lot of area.

2) Use one metal in one direction only; this does not apply for metal 1. Say you are using metal 2 to do horizontal connections, and then use metal 3 for vertical connections, metal4 for horizontal, metal 5 vertical etc...

3) Place as much substrate contact as possible in the empty spaces of the layout.

4) Do not use poly over long distances as it has huge resistances unless you have no other choice.

5) Use fingered transistors as and when you feel necessary.

6) Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner.


11) Give two ways of converting a two input NAND gate to an inverter?


(a) Short the 2 inputs of the NAND gate and apply the single input to it.
(b) Connect the output to one of the input and the other to the input signal.


12) Convert D-FF into divide by 2.What is the max clock frequency the circuit can handle, given the following information?

T_setup= 6nS T_hold = 2nS T_propagation = 10nS

Circuit: Connect Qbar to D and apply the clk at clk of DFF and take the O/P at Q. It gives freq/2. Max.

Freq of operation: 1/ (propagation delay+setup time) = 1/16ns = 62.5 MHz


13) What is false path? Give an example?

Ans: The paths in the circuit, which are never exercised during normal circuit operation for any set of inputs.
Example: give MUX example


14) What are multi-cycle paths? Give example.

Ans: Multi-cycle paths are paths between registers that take more than one clock cycle to become stable.

15) How operating voltage can be used to satisfy timing?

Ans: If multi VDD design then, I feel, we can do something……….. !!


16) How to decide number of pads in chip level design?

Ans: No. of pads= dynamic power / [no. of sides *core voltage * Max current per pad]


17) What is Silicide, salicide, polycide?


Silicide: A fab process


18) Where PVT is referred?



19) Explain ‘slack’ and ‘slew’ with waveforms only.



20) Draw 2 input NOR in transistor level. Draw its layout.



21) Use Euler method to do layout of ((A+B) C)’



22) Draw D latch using MUX.



23) What is spacing, width and overlap rule? Give two examples to each.



24) Why setup is fixed before CTS? Why hold is fixed after CTS?



25) What is the difference between placement and routing congestion?



26) What corner cells contains?

Ans: Nothing………..! It has a metal layer for the continuity of power ground network!


27) What is the difference between core filler cells and metal fillers?

Ans: Core filler cells are used for the continuity of power rails in core area.

Metal fillers are used to avoid Antenna effect. (In DFM).



[1] Sung Mo Kang and Yusuf Leblebici, CMOS digital integrated circuits-analysis and design, Tata McGraw hill, third edition, 2003

[2] Jan M Rabaey & Anantha Chandrakasan & Borivoje Nikolic, Digital integrated circuits-a design perspective, Pearson education, third edition, 2005

[3] Sedra & smith, Microelectronic circuits, oxford university press, fifth edition, 2004


05 July 2007

CMOS Interview Questions

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1. Explain why & how a MOSFET works
2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation
3. Explain the various MOSFET Capacitances & their significance
4. Draw a CMOS Inverter. Explain its transfer characteristics
5. Explain sizing of the inverter
6. How do you size NMOS and PMOS transistors to increase the threshold voltage?
7. What is Noise Margin? Explain the procedure to determine Noise Margin
8. Give the expression for CMOS switching power dissipation
9. What is Body Effect?
10. Describe the various effects of scaling
11. Give the expression for calculating Delay in CMOS circuit
12. What happens to delay if you increase load capacitance?
13. What happens to delay if we include a resistance at the output of a CMOS circuit?
14. What are the limitations in increasing the power supply to reduce delay?
15. How does Resistance of the metal lines vary with increasing thickness and increasing length?
16. You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
17. What happens if we increase the number of contacts or via from one metal layer to the next?
18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
20. Draw the stick diagram of a NOR gate. Optimize it
21. For CMOS logic, give the various techniques you know to minimize power consumption
22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
23. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
24. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
26. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
27. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
29. Draw a 6-T SRAM Cell and explain the Read and Write operations
30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
31. What happens if we use an Inverter instead of the Differential Sense Amplifier?
32. Draw the SRAM Write Circuitry
33. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance?
35. What’s the critical path in a SRAM?
36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
37. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
39. How can you model a SRAM at RTL Level?
40. What’s the difference between Testing & Verification?
41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
1. Give two ways of converting a two input NAND gate to an inverter
2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)
3. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
4. Give a circuit to divide frequency of clock cycle by two
5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
6. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)
7. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this?
8. What are the different Adder circuits you studied?
9. Give the truth table for a Half Adder. Give a gate level implementation of the same.
10. Draw a Transmission Gate-based D-Latch.
11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
12. How do you detect if two 8-bit signals are same?
13. How do you detect a sequence of "1101" arriving serially from a signal line?
14. Design any FSM in VHDL or Verilog.
15. Explain RC circuit’s charging and discharging.
16. Explain the working of a binary counter.
17. Describe how you would reverse a singly linked list.

Intel Interview Questions

DIGITAL/VLSI/ASIC/CMOS interview questions

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1. Insights of an inverter. Explain the working?
2. Insights of a 2 input NOR gate. Explain the working?
3. Insights of a 2 input NAND gate. Explain the working?
4. Implement F= not (AB+CD) using CMOS gates?
5. Insights of a pass gate. Explain the working?
6. Why do we need both PMOS and NMOS transistors to implement a pass gate?
7. What does the above code synthesize to?
8. Cross section of a PMOS transistor?
9. Cross section of an NMOS transistor?
10. What is a D-latch? Write the VHDL Code for it?
11. Differences between D-Latch and D flip-flop?
12. Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?
13. What is latchup? Explain the methods used to prevent it?
14. What is charge sharing?
15. While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?
16. Why is OOPS called OOPS? (C++)
17. What is a linked list? Explain the 2 fields in a linked list?
18. Implement a 2 I/P and gate using Tran gates?
19. Insights of a 4bit adder/Sub Circuit?
20. For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?
21. Explain various adders and diff between them?
22. Explain the working of 4-bit Up/down Counter?
23. A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?
24. Advantages and disadvantages of Mealy and Moore?
25. Id vs. Vds Characteristics of NMOS and PMOS transistors?
26. Explain the operation of a 6T-SRAM cell?
27. Differences between DRAM and SRAM?
28. Implement a function with both ratioed and domino logic and merits and demerits of each logic?
29. Given a circuit and asked to tell the output voltages of that circuit?
30. How can you construct both PMOS and NMOS on a single substrate?
31. What happens when the gate oxide is very thin?
32. What is setup time and hold time?
33. Write a pseudo code for sorting the numbers in an array?
34. What is pipelining and how can we increase throughput using pipelining?
35. Explain about stuck at fault models, scan design, BIST and IDDQ testing?
36. What is SPICE?
37. Differences between IRSIM and SPICE?
38. Differences between netlist of HSPICE and Spectre?
39. What is FPGA?
40. Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?
41. Draw the Layout of an Inverter?
42. If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?
43. Implement F = AB+C using CMOS gates?
44. Working of a 2-stage OPAMP?
45. 6-T XOR gate?
46. Differences between blocking and Non-blocking statements in Verilog?
47. Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?
48. Differences between functions and Procedures in VHDL?
49. What is component binding?
50. What is polymorphism? (C++)
51. What is hot electron effect?
52. Define threshold voltage?
53. Factors affecting Power Consumption on a chip?
54. Explain Clock Skew?
55. Why do we use a Clock tree?
56. Explain the various Capacitances associated with a transistor and which one of them is the most prominent?
57. Explain the Various steps in Synthesis?
58. Explain ASIC Design Flow?
59. Explain Custom Design Flow?
60. Why is Extraction performed?
61. What is LVS, DRC?
62. Who provides the DRC rules?
63. What is validation?
64. What is Cross Talk?
65. Different ways of implementing a comparator?
66. What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
67. What is clock feed through?
68. Implement an Inverter using a single transistor?
69. What is Fowler-Nordheim Tunneling?
70. Insights of a Tri-state inverter?
71. If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
72. Differences between Array and Booth Multipliers?
73. Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
74. Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
75. Insights of a Tri-State Inverter?
76. Basic Stuff related to Perl?
77. Have you studied buses? What types?
78. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
79. How many bit combinations are there in a byte?
80. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
81. Explain the operation considering a two processor computer system with a cache for each processor.
82. What are the main issues associated with multiprocessor caches and how might you solve them?
83. Explain the difference between write through and write back cache.
84. Are you familiar with the term MESI?
85. Are you familiar with the term snooping?
86. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
87. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
88. You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
89. What are the total number of lines written by you in C/C++? What is the most complicated/valuable program written in C/C++?
90. What compiler was used?
91. What is the difference between = and == in C?
92. Are you familiar with VHDL and/or Verilog?
93. What types of CMOS memories have you designed? What were their size? Speed?
94. What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
95. What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
96. Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
97. What types of high speed CMOS circuits have you designed?
98. What transistor level design tools are you proficient with? What types of designs were they used on?
99. What products have you designed which have entered high volume production?
100. What was your role in the silicon evaluation/product ramp? What tools did you use?
101. If not into production, how far did you follow the design and why did not you see it into production?

CMOS Interview Questions

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1. What types of CMOS memories have you designed? What was their size? Speed? Configuration Process technology?
2. What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
3. What types of I/O have you designed? What was their size? Speed? Configuration? Voltage requirements? Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
4. What types of high speed CMOS circuits have you designed?
5. What transistor level design tools are you proficient with? What types of designs were they used on?
6. What products have you designed which have entered high volume production?
7. What was your role in the silicon evaluation/product ramp? What tools did you use?
8. If not into production, how far did you follow the design and why did not you see it into production?

VLSI Interview Questions...... CMOS

VLSI/ASIC/CMOS/Digital Interview Questions

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1. What happens if Vds is increased over saturation?
Ans:Pinch off
2. In the I-V characteristics curve, why is the saturation curve flat or constant?
Ans: no consideration of channel length modulation
3. What happens if a resistor is added in series with the drain in a mos transistor?
4. What are the different regions of operation in a mos transistor?
5. What are the effects of the output characteristics for a change in the beta (β) value?
6. What is the effect of body bias?
7. What is hot electron effect and how can it be eliminated?
8. What is latchup problem and how can it be eliminated?
9. What is channel length modulation?
10. What is the effect of temperature on threshold voltage?
11. What is the effect of temperature on mobility? What is the effect of gate voltage on mobility?
12. What are the different types of scaling?
13. What is stage ratio?
14. What is charge sharing on a bus?
15. What is electron migration and how can it be eliminated?
16. Can both pmos and nmos transistors pass good 1 and good 0? Explain.
17. Why is only nmos used in pass transistor logic?
18. What are the different methodologies used to reduce the charge sharing in dynamic logic?
19. What are setup and hold time violations? How can they be eliminated?
20. Explain the operation of basic sram and dram.
21. Of Read and Write operations, which ones take more time? Explain.
22. What is meant by clock race?
23. What is meant by single phase and double phase clocking?
24. If given a choice between NAND and NOR gates, which one would you pick?
25. What are stuck-at faults?
26. What is meant by ATPG?
27. What is meant by noise margin in an inverter? How can you overcome it?
28. Why is size of pmos transistor chosen to be close to three times of an nmos transistor?
29. Explain the origin of the various capacitances in the mos transistor and the physical reasoning behind it.
30. Why should the number of CMOS transistors that are connected in series be reduced?
31. What is charge sharing between bus and memory element?
32. What is crosstalk and how can it be avoided?
33. Two inverters are connected in series. The widths of pmos and nmos transistors of the second inverter are 100 and 50 respectively. If the fan-out is assumed to be 3, what would be the widths of the transistors in the first inverter?
34. In the above situation, what would be the widths of the transistors if the first inverter is replaced by NAND and NOR gates?
35. What is the difference between a latch and flip-flop? Give examples of the applications of each.
36. Realize an XOR gate using NAND gate.
37. What are the advantages and disadvantages of Bi-CMOS process?
38. Draw an XOR gate with using minimal number of transistors and explain the operation.
39. What are the critical parameters in a latch and flip-flop?
40. What is the significance of sense amplifier in an SRAM?
41. Explain Domino logic.
42. What are the differences between PALs, PLAs, FPGAs, ASICs and PLDs?
43. What are the advantages of depletion mode devices over the enhancement mode devices?
44. How can the rise and fall times in an inverter be equated?
45. What is meant by leakage current?
46. Realize an OR gate using NAND gate.
47. Realize an NAND gate using a 2:1 multiplexer.
48. Realize an NOR gate using a 2:1 multiplexer.
49. Draw the layout of a simple inverter.
50. What are the substrates of pmos and nmos transistors connected to and explain the results if the connections are interchanged with the other.
51. What are repeaters in VLSI design?
52. What is meant by tunneling problem?
53. What is meant by negative biased instability and how can it be avoided?
54. What is Elmore delay algorithm?
55. What are false and multi cycle paths?
56. What is meant by metastability?
57. What are the various factors that need to be considered while choosing a technology library for a design?
58. What is meant by clock skew and how can it be avoided?
59. When stated as 0.13μm CMOS technology, what does 0.13 represent?
60. What is the effect of Vdd on delay?
61. What are the various limitations in changing the voltage for less delay?
62. What is the difference between testing and verification?
63. While trying to drive a huge load, driver circuits are designed with number of stages with a gradual increase in sizes. Why is this done so? What not use just one big driver gate?
64. What is the effect of increase in the number of contacts and vias in the interconnect layers?
65. How does the resistance of the metal layer vary with increasing thickness and increasing length?
66. What is the effect of delay, rise and fall times with increase in load capacitance?
67. In a simple inverter circuit, if the pmos in the Pull-Up Network is replaced by an nmos and if the nmos in the Pull-Down Network is replaced by a pmos transistor, will the design work as an non-inverting buffer? Justify your answer.
68. What is mobility of electrons?
69. What is mobility of holes?

04 July 2007

SRAM Cell Design

1.1 Introduction

Starting from the design specification to the generation of mask layout, layout design of an integrated circuit has several processing steps which have to be carefully exercised. These steps include design of transistor level schematic, SPICE simulation of the circuit according to the designed W/L ratios of the individual transistors, drawing of the layout using a layout editor, design rule check, parasitic extraction and final simulation and verification. These all processing methods are inevitable for the error free operation of chip and similar methodology is followed for the design of 1 KByte SRAM IC. Basic building block of the SRAM is SRAM cell which stores one bit data. Using common bit lines data can be read and written to the SRAM cell. SPICE, being an industry standard tool for circuit simulation and analysis, is used for the simulation and analysis of SRAM cell and subsequently for the whole design. Precharge circuit, sense amplifier and read-write circuits completes the one SRAM memory. The memory is arranged in row- column matrix which facilitates easy addressing of memory bits and also provides design flexibility. Once the functionality of one memory cell array is proved it can be duplicated several times with minor design change in the I/O control circuitry.

1.2 Plan of the chip

Block diagram of the complete chip is shown in Figure(1.1).Six transistor SRAM cells are organised into 8 blocks. The capacity of the SRAM cell is 1 Kbyte. To address all these locations total 10 address lines from A0 to A9 are used. Out of these, A0 to A2 are used as column address decoding lines while A3 to A9 are used for decoding the rows. Each row consists total 8 memory cells and constitute to form one byte. Thus address lines address each byte not the each bit.

Each block is comprised of 128 rows and 8 columns. Thus the total number of transistors required for memory cells are 6 transistors x 128 rows x 8 columns x 8 blocks = 49,152. Rows of the each block are decoded using NOR based 7 x128 decoder. Total 1024 transistors are required for this circuit. Row decoder outputs are connected to the each row of the each block. Similarly each block is selected by the 3 x 8 column decoder. This requires total 32 transistors.

Figure (1.1) SRAM block diagram [4]

Sense amplifier is used to sense the data present in the memory cell. Input and output data control block consists of read and write circuitry and related driver circuits. 8 bits of the data D0 to D7 is read or written parelell. Read enable (RE) and write enable (WE) are the two control lines available for the chip. As the name indicate, before data read operation is performed RE is activated for read operations. Similarly for write operations WE signal has to be enabled.

Table(1.1) transistors required for different blocks

Table (1.1) summarises the total number of transistors required for each individual block of the SRAM memory. 1.8V is assumed for the chip power supply internally as well as externally.

1.3 SRAM cell: schematic and working

Figure (1.2) Schematic of SRAM cell

Single bit SRAM memory cell is shown in Figure (1.2). Static latches are used in the SRAM cell. SRAM cell is made up of flip flop comprising of two cross coupled inverters. Two access transistors are used to access the stored data in the cell. These transistors are turned ON/OFF by the control line called word line(WL). Generally this word line is connected to the output of row decoder circuits. When WL=VDD the SRAM cell is connected to bit line(BL) and complement of bit line (BLbar) allowing both read and write operations. Read-write operation is carried out by the help of access transistors.

Read operation:

Consider node Y as reference node of the SRAM cell. Cell is said to be storing 1 if node Y is high at VDD and node Ybar is at 0V. For the reverse voltage conditions cell is said to be storing zero. Let us assume that cell is storing 1.Before the read operation starts BL and BLbar lines are precharged to VDD/2. When the WL is activated the current flows through M5 and M6. Now current from VDD will flow through M1 and M5 charging the bit line capacitance, say CBL. The existing capacitance on the line BLbar, say CBLbar discharges through the transistors M6 and M4. This process develops a voltage difference between node Y and node Ybar which is sensed by the sense amplifier to detect it as 1. Similarly a 0 in the cell is also detected by the sense amplifier.

Write operation:

Let us consider the write operation of zero to the cell which is storing a value of 1. For this, sense amplifiers and precharge circuits are disabled. The cell is selected by activating the corresponding WL signal. To write zero to the cell, BL line held low and BLbar line is raised to VDD by the write circuit. Thus the node Ybar is pulled up towards the VDD/2 while node Y is pulled down to VDD/2. When the voltage crosses this level on two nodes feedback action starts. Parasitic capacitances developed by M3, M5 and M4, M6 are charged and discharged respectively. Ultimately node Y stabilises at the value 1. Since these parasitic capacitances offered by transistors are comparatively much lesser than the bit line capacitances, write operation is faster than read operation.

Transistor sizing:

The W/L ratio of the transistor is selected to provide the gate with current driving capability in both the directions equal to that of the basic inverter. From the basic inverter design (W/L)n is usually 1.5 to 2 and for a matched design, (W/L)p=(µnp)(W/L)n. The SRAM cell must be designed such a way that, during read operation, the changes in Y and Ybar are small enough to prevent the cell from changing its state. Generally two back to back coupled inverters of the SRAM cell is designed so that Kn and Kp are matched. This design places the inverter threshold at VDD/2. The size of the access transistors are usually made 2 to 3 times wider than Kn of the inverters.

To achieve optimum operation of the cell following (W/L) ratio is choosed for different transistors. A minimum ratio of 2 is required for NMOS transistors of inverters and 4 is necessary for PMOS transistors. Access transistors must be made double wider or more by providing a W/L ratio of more than 4. But these set of ratios does not match with the design rule of Cadence Virtuoso layout editor for 0.18 micron technology. For 0.18 µ technology minimum width for an NMOS transistor comes out to be 0.6 µ. Thus (W/L) ratio is 3.33. For PMOS transistor the ratio becomes 6.66. This implies a width of 1.2 µ. Based on the SPICE simulation results and its analysis, W/L ratio for access transistor is kept at 9.99. This refers to a gate width of 1.8 µ.

1.4 Simulation

Mainly two types of simulation analysis is reported here. The first one focusses on normal operation of SRAM cell with approapriate W/L ratio. The second simulation studies the affect of variation of W/L ratio of access transistor on the working of SRAM cell.

Simulation 1:

Figure (1.3) shows the SPICE simulation waveform of the SRAM cell. For 0.18 µ technology, the gate width choosed for NMOS transistors are 0.6 µ; for PMOS it is 1.2 V and for access transistors gate width is 1.8 µ. When WL is disabled(i.e. low) SRAM cell is disconnected from the BL and BLbar lines. Hence voltage at node Y and Ybar is complement to each other and remains in a stable state. The stable state value is dependant on the previous value present at BL and BLbar lines.

BL signal is forced with pulse waveform of period 8ns and pulse width of 4ns. Upon activation of WL signal SRAM cell gets connected with BL and BLbar signal.

Figure (1.3) SRAM cell SPICE simulation waveform 1

Now the expected waveform at the BLbar is the inverted signal of BL. The same result can be seen in simulation waveform 1. Voltage at node Y follow the pulse voltage of BL; and node Ybar and BLbar are same and complement to pulse signal at BL.

Removal of WL again disconnects the SRAM cell from the BL and BLbar line. SRAM cell holds the value whatever it had while removing the WL signal.

Simulation 2:

If W/L ratio of access transistors is reduced to the ratio of PMOS transistors then the cell fails to operate as expected due to the inefficient current driving capability of access transistor. Related waveform is shown in Figure (1.4). Here for access transistors W/L ratio is set same as that of PMOS transistor i.e. 6.66 which implies a gate width of 1.2 µ. Observe the waveform shape at area marked by circles. The waveform at BLbar should be complement to waveform at BL. But it is remaining at high state.

Figure (1.4) SRAM cell SPICE simulation waveform 2

This is due to the poor switching of access transistor. Similar waveforms can be observed at node Y and Ybar. (Outputs of cross coupled inverters).

1.5 Layout of the SRAM cell

Layout is a physical representation of a schematic. A set of geometric constraints or rules for a particular manufacturing process has to be followed for the physical mask layout generation. Geometries are determined by the electrical properties of the devices and design rules pertaining to the associated manufacturing process.

The mask layout design of CMOS logic gate or cell starts with the functionality and performance specification of the cell to be designed and ends in the layout. The specifications include circuit topology and initial size of the transistor. The designed transistor level schematic is simulated by the help of SPICE simulation tools. If simulation does not satisfy the required specification architecture and schematic design is revised. Optimum ordering of the transistors is determined by the Euler path method. Stick diagram representation is drawn which shows the location of the transistors, local intersections between transistors and location of the contacts. Mask layers are formed using a layout editor tool. After several iterations of editing and design rule check (DRC) and layout versus schematic (LVS) check the layout is subjected to extraction procedure. Extraction procedure extracts parasitic capacitance values and actual sizes of the transistors.

Figure (1.5) SRAM cell layout

(This is not a optimized layout...or rather not even followed basic rules !!! It just demonstrates how to draw a layout !!)

SPICE file is automatically generated consisting of all these parasitic capacitance values and other device parameters. This netlist is simulated using a SPICE simulator and verified for the designed specification. If this doesn’t match the whole process is repeated from the scratch.

Design rules include geometric constraints and line width constraints. The later defines constraints like metal and polysilicon interconnection, diffusion area, minimum feature dimensions and allowable separations between two different features. Mainly there are two ways of design rules. They are known as micron rules and lambda rules. In micron rule all layout constraints are defined in micrometers while in lambda rule it is defined in terms of a single parameter lambda (λ). For the present assignment micron rules are used.

Design specifications of the SRAM cell and its corresponding SPICE simulation results have been studied in the previous sections. For the SRAM cell layout shown in the Figure (1.5) first we need to design the individual transistors according to the design rules. PMOS transistors are placed in an n-well region whereas NMOS transistors are placed directly above the substrate. Transistors M1 to M6 are placed. Polysilicon gate of both NMOS and PMOS transistors of cross coupled inverters (i.e. latch) are aligned so that polysilicon length is minimized to reduce parasitic resistance and capacitance. Metal 1 and metal 2 layer is used for the interconnections between transistors. Metal 1 is used for direct interconnections and wherever the connections crisscross metal 2 layer is used. Bit line (BL) and bit linebar(BLbar) are vertically drawn with metal 1 layer while word line(WL), vdd and gnd are drawn horizontally with metal 2 layer. This layout method helps to extend SRAM memory by adding more SRAM cells.

From the layout Figure (1.5) it can be noted that total area of the SRAM cell can be further reduced by using optimization methods (like Euler method). Since basic motto of this SRAM cell design is to understand the layout methodology no optimization effort is put.

1.6 SRAM cell array: schematic and working

Figure (1.6) shows a cell array SRAM which comprises of total eight cells organized into one row and 8 columns. Number of cells in each column can be extended to 128 or more than that depending on the specification of the SRAM. In addition to SRAM cells, supporting circuits like sense amplifiers and precharge and equalization circuits are connected to BL and BLbar lines of columns. To test working of 3x8 decoder along with memory cells, instead of addressing whole 8 bits by one address, each column is addressed by each output of decoder.

BL and BLbar signals are connected to internal data lines. Read driver circuit has these DL and DLbar lines as its input and output is connected to chip data I/O pin. For the write circuitry chip I/O becomes input and DL and DLbar lines become output.

Figure (1.6) SRAM cell array

The same circuit can be extended to 128x8 block memory. This can be accomplished by adding additional SRAM cells in each column. Total 128 SRAM cells can be added in a column. These cells are addressed by a 7x128 row decoder. The outputs of row decoder from R0 to R127 are connected to word lines of individual row SRAM cells. All WL of each row SRAM cells are tied together. Thus with the help of total 10 address bits we can address whole 128x8 block of 210=1024 bits. To make simulation process and analysis simple, only one row and 8 columns (i.e. total 8 SRAM cells) is constructed. Once it is proved that this cell array works as expected then the same concept can be extended for higher size of SRAM.

The precharge transistors used above SRAM cells in Figure (1.6) can be omitted if precharge block is used and vice versa. Precharge circuit speeds up the read operation. Sense amplifier is used to sense the data available in the SRAM cell. The working and simulation analysis of sense amplifier, precharge circuit and address decoder are discussed in detail in Chapter 2.

Read operation:

At startup both decoders are inactive. As soon as decoders are enabled either by separate address enable signal or chip enable signal, they are precharged first. This process makes all output high for a small amount of time. This address is invalid. Then address settles down according to the input of the decoder and one particular SRAM cell is activated.

To begin the read operation, precharge circuit is enabled by activating PE for a small amount of time and then disabled. This process precharges BL and BLbar lines to either VDD or VDD/2 depending on the precharge circuit used. To sense the voltage difference established at BL and BLbar, sense amplifier is enabled. Sense amplifier reinforces the state of the BL and BLbar lines. Activation of read enable (RE) signal enables the read buffer. Since BL and BLbar lines are commonly connected DL and DLbar lines and these two signals are input to read buffer. The read SRAM cell data traverses towards read buffer. The read buffer reads both DL and DLbar lines and outputs the data available in DL line. Thus the data bit is read from memory cell. To continue the read operation address bits are changed to address the next memory cell. Precharge is activated and then deactivated. Since sense amplifier and read buffer is already activated read data is immediately available at the output of the buffer.

For simulation PE, SE and RE are separately forced. But in practical cases taking all these enable signals to chip I/O may not be efficient design strategy. A single read enable signal is provided for the chip. One more circuitry has to be added which provides sufficient delay between PE, SE and RE so that all circuits are enabled one by one.

Write operation:

For the write operation PE, SE and RE signal is disabled which disables all read related circuits from interacting with SRAM cell. The address is selected and data is given to write circuit as input. Upon the activation of write enable (WE) signal, write buffer output change according to the input. The outputs are connected to DL and DLbar lines and hence BL and BLbar lines, both signals are forced to change to a new value. The feedback action in SRAM cell then stabilizes the data of the memory. WE signal is then disabled for safe write operation and to avoid further writing of spurious data. To continue the write operation to other cells address bits are changed and same procedure is repeated.

1.7 Conclusion

Single bit SRAM cell is designed and simulated. From the simulation and related analysis it is found that access transistor size plays vital role in the memory bit design. The latch transistors should be matched and access transistors must be twice of the PMOS transistor size. Layout is drawn and area required is approximately 1µ x 0.7 µ. Applying optimization methods will reduce the area required for the cell. Further study and analysis of extracted parasitic values and its affect on circuit functionality will prove beneficial to include the cell in a standard cell library.


[1] Sung Mo Kang and Yusuf Leblebici, CMOS digital integrated circuits-analysis and design, Tata McGraw hill, third edition, 2003

[2] Jan M Rabaey & Anantha Chandrakasan & Borivoje Nikolic, Digital integrated circuits-a design perspective, Pearson education, third edition, 2005

[3] Sedra & smith, Microelectronic circuits, oxford university press, fifth edition, 2004

[4] One KByte SRAM chip Specifications and Design Plan