11 October 2007

ASIC General

General ASIC questions are posted here. More questions related to different catagories of ASICs can be found at respective sections.

  • What are the differences between PALs, PLAs, FPGAs, ASICs and PLDs?
  • In system with insufficient hold time, will slowing down the clock help?
  • In system with insufficient setup time, will slowing down the clock help?
  • Why would a testbench not have pins (port) on it?
  • When declaring a flip flop, why would not you declare its output value in the port statement?
  • Give 2 advantages of using a script to build a chip?
  • A “tri state “ bus is directly connected to a set of CMOS input buffers. No other wires or components are attached to the bus wires. Upon observation we can find that under certain conditions, this circuit is consuming considerable power. Why it is so? Is circuit correct? If not, how to correct?
  • Is Verilog (or that matter any HDL) is a concurrent or sequential language?
  • What is the function of sensitivity list?
  • A mealy –type state machine is coded using D-type rising edge flip flops. The reset and clock signals are in the sensitivity list but with one of the next state logic input signals have been left out of the sensitivity list. Explain what happens when the state machine is simulated? Will the state machine be synthesized correctly?
  • A moore –type state machine is coded using D-type rising edge flip flops. The reset and clock signals are in the sensitivity list but with one of the next state logic input signals have been left out of the sensitivity list. Explain what happens when the state machine is simulated? Will the state machine be synthesized correctly?
  • What type of delay is most like a infinite bandwidth transmission line?
  • Define metastability.
  • When does metastability occur?
  • Give one example of a situation where metastability could occur.
  • Give two ways metastability could manifest itself in a state machine.
  • What is MTBF?
  • Does MTBF give the time until the next failure occurs?
  • Give 3 ways in which to reduce the chance of metastable failure.
  • Give 2 advantages of using a synchronous reset methodology.
  • Give 2 disadvantages of using a synchronous reset methodology.
  • Give 2 advantages of using an asynchronous reset methodology.
  • Give 2 disadvantages of using an asynchronous reset methodology.
  • What are the two most fundamental inputs (files) to the synthesis tool?
  • What are two important steps in synthesis? What happens in those steps?
  • What are the two major output (files) from the synthesis process?
  • Name the fundamental 3 operating consitions that determine (globally) the delay characteristics of CMOS gates. For each how they affect gate delay?
  • For a single gate, with global gating conditions held constant , what 3 delay coefficients effect total gate delay? Which is the most sensitive to circuit topology?







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