21 October 2007

ASIC Design Check List

Silicon Process and Library Characteristics
  • What exact process are you using?
  • How many layers can be used for this design?
  • Are the Cross talk Noise constraints, Xtalk Analysis configuration, Cell EM & Wire EM available?

Design Characteristics

  • What is the design application?
  • Number of cells (placeable objects)?
  • Is the design Verilog or VHDL?
  • Is the netlist flat or hierarchical?
  • Is there RTL available?
  • Is there any datapath logic using special datapath tools?
  • Is the DFT to be considered?
  • Can scan chains be reordered?
  • Is memory BIST, boundary scan used on this design?
  • Are static timing analysis constraints available in SDC format?


Clock Characteristics

  • How many clock domains are in the design?
  • What are the clock frequencies?
  • Is there a target clock skew, latency or other clock requirements?
  • Does the design have a PLL?
  • If so, is it used to remove clock latency?
  • Is there any I/O cell in the feedback path?
  • Is the PLL used for frequency multipliers?
  • Are there derived clocks or complex clock generation circuitry?
  • Are there any gated clocks?
  • If yes, do they use simple gating elements?
  • Is the gate clock used for timing or power?
  • For gated clocks, can the gating elements be sized for timing?
  • Are you muxing in a test clock or using a JTAG clock?
  • Available cells for clock tree?
  • Are there any special clock repeaters in the library?
  • Are there any EM, slew or capacitance limits on these repeaters?
  • How many drive strengths are available in the standard buffers and inverters?
  • Do any of the buffers have balanced rise and fall delays?
  • Any there special requirements for clock distribution?
  • Will the clock tree be shielded? If so, what are the shielding requirements?

Floorplan and Package Characteristics

  • Target die area?
  • Does the area estimate include power/signal routing?
  • What gates/mm2 has been assumed?
  • Number of routing layers?
  • Any special power routing requirements?
  • Number of digital I/O pins/pads?
  • Number of analog signal pins/pads?
  • Number of power/ground pins/pads?
  • Total number of pins/pads and Location?
  • Will this chip use a wire bond package?
  • Will this chip use a flip-chip package?
  • If Yes, is it I/O bump pitch? Rows of bumps? Bump allocation?Bump pad layout guide?
  • Have you already done floorplanning for this design?
  • If yes, is conformance to the existing floorplan required?
  • What is the target die size?
  • What is the expected utilization?
  • Please draw the overall floorplan ?
  • Is there an existing floorplan available in DEF?
  • What are the number and type of macros (memory, PLL, etc.)?
  • Are there any analog blocks in the design?
  • What kind of packaging is used? Flipchip?
  • Are the I/Os periphery I/O or area I/O?
  • How many I/Os?
  • Is the design pad limited?
  • Power planning and Power analysis for this design?
  • Are layout databases available for hard macros ?
  • Timing analysis and correlatio?
  • Physical verification ?
Data Input
  • Library information for new library
  • .lib for timing information
  • GDSII or LEF for library cells including any RAMs
  • RTL in Verilog/VHDL format
  • Number of logical blocks in the RTL
  • Constraints for the block in SDC
  • Floorplan information in DEF
  • I/O pin location
  • Macro locations

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