27 September 2007

Power Gating

Power gating is the technique wherein circuit blocks that are not in
use are temporarily turned off to reduce the overall leakage power of
the chip. This temporary shutdown time can also called as "low power
mode" or "inactive mode". When circuit blocks are required for
operation once again they are activated to "active mode". These two
modes are switched at the appropriate time and in the suitable manner
to maximize power performance while minimizing impact to performance.
Thus goal of power gating is to minimize leakage power by temporarily
cutting power off to selective blocks that are not required in that

Power gating affects design architecture more compared to the clock
. It increases time delays as power gated modes have to be
safely entered and exited. The possible amount of leakage power saving
in such low power mode and the energy dissipation to enter and exit
such mode introduces some architectural trade-offs.

How to shut down the blocks? It can be accomplished either by software
or hardware. Driver software can schedule the power down operations.
Hardware timers can be utilized. A dedicated power management
controller is the other option.

An externally switched power supply is very basic form of power gating
to achieve long term leakage power reduction. To shutoff the block for
small interval of time internal power gating is suitable. CMOS
switches that provide power to the circuitry are controlled by power
gating controllers.

Output of the power gated block discharge slowly. Hence output voltage
levels spend more time in threshold voltage level. This can lead to
larger short circuit current.

Isolation Cells

Isolation cells are used to prevent short circuit current. As the name
indicates these cells isolate power gated block from the normally on
block. Isolation cells are specially designed for low short circuit
current when input is at threshold voltage level. Isolation control
signals are provided by power gating controller.

Retention Registers

Retention registers are special low leakage flip-flops used to hold
the the data of main register of the power gated block. Thus internal
state of the block during power down mode can be retained and loaded
back to it when the block is reactivated. retention registers are
always powered up. The retention strategy is design dependent. During
the power gating data can be retained and transfered back to block when
power gating is withdrawn. Power gating controller controls the
retention mechanism such as when to save the current contents of the
power gating block and when to restore it back.

Related Articles

Low Power Techniques: Clock Gating

Low Power Techniques: Multi Voltage

Low Power Techniques: Multiple Threshold Cell Libraries


Michael Keating, David Flynn, Robert Aitken, Alan Gibbons, Kaijian
Shi,"Low Power Methodology Manual For System on Chip Design",
Electronic Edition,Springer, 2007. www.lpmm-book.org

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